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1. 发明申请

US20120228640A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120228640A1
公开(公告)日：2012-09-13
申请号：US13512456
申请日：2011-07-14
申请人： Takeyoshi Masuda , Shin Harada , Misako Honaga , Keiji Wada , Toru Hiyoshi
发明人： Takeyoshi Masuda , Shin Harada , Misako Honaga , Keiji Wada , Toru Hiyoshi
IPC分类号： H01L29/24 , H01L21/04
CPC分类号： H01L29/66068 , H01L21/046 , H01L21/0475 , H01L21/3065 , H01L29/045 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/1608 , H01L29/4236 , H01L29/6606 , H01L29/7397 , H01L29/7813 , H01L29/8613 , H01L29/868
摘要： There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes: a substrate having a main surface; and a silicon carbide layer formed on the main surface of the substrate and including a side surface inclined relative to the main surface. The side surface substantially includes a {03-3-8} plane. The side surface includes a channel region.
摘要翻译：提供了具有稳定特性的高质量半导体器件和制造这种半导体器件的方法。半导体器件包括：具有主表面的衬底; 以及形成在所述基板的主表面上并且包括相对于所述主表面倾斜的侧表面的碳化硅层。侧表面基本上包括{03-3-8}平面。侧面包括通道区域。

2. 发明授权

US08564017B2 Silicon carbide semiconductor device and method for manufacturing same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US08564017B2
公开(公告)日：2013-10-22
申请号：US13485423
申请日：2012-05-31
申请人： Misako Honaga , Takeyoshi Masuda , Keiji Wada , Toru Hiyoshi
发明人： Misako Honaga , Takeyoshi Masuda , Keiji Wada , Toru Hiyoshi
IPC分类号： H01L29/66 , H01L21/337 , H01L29/15
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/1095 , H01L29/66068
摘要： A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N1d for a first conductivity type. A body region is provided on a portion of the drift layer, has a channel to be switched by a gate electrode, has an impurity concentration N1b for the first conductivity type, and has an impurity concentration N2b for the second conductivity type greater than the impurity concentration N1b. A JFET region is disposed adjacent to the body region on the drift layer, has an impurity concentration N1j for the first conductivity type, and has an impurity concentration N2j for the second conductivity type smaller than the impurity concentration N1j. N1j−N2j>N1d and N2j
摘要翻译：漂移层具有电流流动的厚度方向，并具有用于第一导电类型的杂质浓度N1d。身体区域设置在漂移层的一部分上，具有由栅电极切换的通道，具有用于第一导电类型的杂质浓度N1b，并且具有大于杂质的第二导电类型的杂质浓度N2b 浓度N1b。 JFET区域与漂移层上的体区附近配置，对于第一导电类型具有杂质浓度N1j，并且对于第二导电类型的杂质浓度N2j小于杂质浓度N1j。 N1j-N2j> N1d和N2j

3. 发明申请

US20120313112A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120313112A1
公开(公告)日：2012-12-13
申请号：US13490208
申请日：2012-06-06
申请人： Keiji Wada , Takeyoshi Masuda , Misako Honaga , Toru Hiyoshi
发明人： Keiji Wada , Takeyoshi Masuda , Misako Honaga , Toru Hiyoshi
IPC分类号： H01L29/161
CPC分类号： H01L29/7802 , H01L29/045 , H01L29/0634 , H01L29/1095 , H01L29/1608 , H01L29/41741 , H01L29/4236 , H01L29/45 , H01L29/66068 , H01L29/7813
摘要： A MOSFET includes a silicon carbide substrate, a drift layer made of silicon carbide and including a main surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, and a gate oxide film formed on and in contact with the main surface of the drift layer. The drift layer includes a p type body region formed to include a region in contact with the gate oxide film. The p type body region has an impurity density of 5×1016 cm−3 or more. A plurality of p type regions of p conductivity type located apart from one another in a direction perpendicular to a thickness direction of the drift layer are arranged in a region in the drift layer lying between the p type body region and the silicon carbide substrate.
摘要翻译： MOSFET包括碳化硅衬底，由碳化硅制成的漂移层，并且包括相对于{0001}面具有50°以上且65°以下的偏离角的主表面，以及形成在并与漂移层的主表面接触。漂移层包括形成为包括与栅氧化膜接触的区域的p型体区。 p型体区的杂质浓度为5×10 16 cm -3以上。在垂直于漂移层的厚度方向的方向上彼此分离的p导电类型的多个p型区域布置在位于p型体区域和碳化硅衬底之间的漂移层中的区域中。

4. 发明授权

US08610131B2 Silicon carbide insulated-gate bipolar transistor 有权
标题翻译：碳化硅绝缘栅双极晶体管
公开(公告)号：US08610131B2
公开(公告)日：2013-12-17
申请号：US13435863
申请日：2012-03-30
申请人： Keiji Wada , Takeyoshi Masuda , Misako Honaga , Toru Hiyoshi
发明人： Keiji Wada , Takeyoshi Masuda , Misako Honaga , Toru Hiyoshi
IPC分类号： H01L29/15
CPC分类号： H01L29/7397 , H01L21/0475 , H01L21/049 , H01L29/045 , H01L29/1608 , H01L29/4236 , H01L29/66068
摘要： An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×1016 cm−3 or more.
摘要翻译： IGBT包括设置在碳化硅半导体层中的沟槽，设置在碳化硅半导体层中的第一导电类型的主体区域以及至少覆盖该沟槽的侧壁表面的绝缘膜，槽的侧壁表面为相对于{0001}面具有偏离角度为50°以上且65°以下的表面，所述凹槽的侧壁表面包括所述主体区域的表面，所述绝缘膜至少与所述表面接触在所述槽的侧壁面的所述主体区域中，所述体区的第一导电型杂质浓度为5×10 16 cm -3以上。

5. 发明申请

US20120248462A1 IGBT 有权
公开(公告)号：US20120248462A1
公开(公告)日：2012-10-04
申请号：US13435863
申请日：2012-03-30
申请人： Keiji Wada , Takeyoshi Masuda , Misako Honaga , Toru Hiyoshi
发明人： Keiji Wada , Takeyoshi Masuda , Misako Honaga , Toru Hiyoshi
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L21/0475 , H01L21/049 , H01L29/045 , H01L29/1608 , H01L29/4236 , H01L29/66068
摘要： An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×1016 cm−3 or more.
摘要翻译： IGBT包括设置在碳化硅半导体层中的沟槽，设置在碳化硅半导体层中的第一导电类型的主体区域以及至少覆盖该沟槽的侧壁表面的绝缘膜，槽的侧壁表面为相对于{0001}面具有偏离角度为50°以上且65°以下的表面，所述凹槽的侧壁表面包括所述主体区域的表面，所述绝缘膜至少与所述表面接触在所述槽的侧壁面的所述主体区域中，所述体区的第一导电型杂质浓度为5×10 16 cm -3以上。

6. 发明授权

US09000447B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US09000447B2
公开(公告)日：2015-04-07
申请号：US13613838
申请日：2012-09-13
申请人： Keiji Wada , Takeyoshi Masuda , Toru Hiyoshi
发明人： Keiji Wada , Takeyoshi Masuda , Toru Hiyoshi
IPC分类号： H01L29/15 , H01L21/04 , H01L29/66 , H01L29/04 , H01L29/78 , H01L29/16 , H01L29/423 , H01L29/06
CPC分类号： H01L21/0475 , H01L21/049 , H01L29/045 , H01L29/0623 , H01L29/1608 , H01L29/36 , H01L29/4236 , H01L29/66068 , H01L29/7813
摘要： A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D1 is defined to represent a location in the first layer away from an interface between the first layer and the second layer in a depth direction. D1 in which 1≦ND/NA≦50 is satisfied is within 1 μm therefrom. A gate trench is provided to extend through the third layer and the second layer to reach the first layer. A gate insulating film covers a side wall of the gate trench. A gate electrode is embedded in the gate trench with the gate insulating film interposed therebetween.
摘要翻译：第一层具有n型导电性。第二层外延形成在第一层上并具有p型导电性。第三层位于第二层上，具有n型导电性。 ND被定义为表示供体型杂质的浓度。 NA被定义为表示受体型杂质的浓度。 D1被定义为在深度方向上表示远离第一层和第二层之间的界面的第一层中的位置。其中满足1＆nlE; ND / NA＆nlE; 50的D1在其1μm以内。提供栅极沟槽以延伸穿过第三层和第二层以到达第一层。栅极绝缘膜覆盖栅极沟槽的侧壁。栅极电极嵌入栅极沟槽中，栅极绝缘膜插入其间。

7. 发明申请

US20130078771A1 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：US20130078771A1
公开(公告)日：2013-03-28
申请号：US13613858
申请日：2012-09-13
申请人： Toru Hiyoshi , Takeyoshi Masuda , Keiji Wada
发明人： Toru Hiyoshi , Takeyoshi Masuda , Keiji Wada
IPC分类号： H01L21/331
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/7395
摘要： A collector layer having p type is formed on a silicon carbide substrate having n type. A drift layer having n type is formed on a top surface side of the collector layer. A body region provided on the drift layer and having p type, and an emitter region provided on the body region to be separated from the drift layer by the body region and having n type are formed. A bottom surface side of the collector layer is exposed by removing the silicon carbide substrate.
摘要翻译：具有p型的集电极层形成在具有n型的碳化硅衬底上。在集电体层的顶面侧形成有n型漂移层。设置在漂移层上并具有p型的体区，并且形成设置在身体区域上以通过身体区域与移动层分离并具有n型的发射极区域。通过去除碳化硅衬底来暴露集电极层的底表面侧。

8. 发明申请

US20130075759A1 SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：US20130075759A1
公开(公告)日：2013-03-28
申请号：US13613838
申请日：2012-09-13
申请人： Keiji Wada , Takeyoshi Masuda , Toru Hiyoshi
发明人： Keiji Wada , Takeyoshi Masuda , Toru Hiyoshi
IPC分类号： H01L29/161
CPC分类号： H01L21/0475 , H01L21/049 , H01L29/045 , H01L29/0623 , H01L29/1608 , H01L29/36 , H01L29/4236 , H01L29/66068 , H01L29/7813
摘要： A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D1 is defined to represent a location in the first layer away from an interface between the first layer and the second layer in a depth direction. D1 in which 1≦ND/NA≦50 is satisfied is within 1 μm therefrom. A gate trench is provided to extend through the third layer and the second layer to reach the first layer. A gate insulating film covers a side wall of the gate trench. A gate electrode is embedded in the gate trench with the gate insulating film interposed therebetween.
摘要翻译：第一层具有n型导电性。第二层外延形成在第一层上并具有p型导电性。第三层位于第二层上，具有n型导电性。 ND被定义为表示供体型杂质的浓度。 NA被定义为表示受体型杂质的浓度。 D1被定义为在深度方向上表示远离第一层和第二层之间的界面的第一层中的位置。其中满足1＆nlE; ND / NA＆nlE; 50的D1在其1μm以内。提供栅极沟槽以延伸穿过第三层和第二层以到达第一层。栅极绝缘膜覆盖栅极沟槽的侧壁。栅极电极嵌入栅极沟槽中，栅极绝缘膜插入其间。

9. 发明申请

US20130065384A1 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：US20130065384A1
公开(公告)日：2013-03-14
申请号：US13613785
申请日：2012-09-13
申请人： Toru Hiyoshi , Takeyoshi Masuda , Keiji Wada
发明人： Toru Hiyoshi , Takeyoshi Masuda , Keiji Wada
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/02529 , H01L21/0262 , H01L21/0475 , H01L21/3065 , H01L21/3081 , H01L29/045 , H01L29/0623 , H01L29/1608 , H01L29/4236 , H01L29/4238 , H01L29/66068 , H01L29/7397
摘要： A mask layer is formed on a silicon carbide layer by a deposition method. The mask layer is patterned. A gate trench having a side wall is formed by removing a portion of the silicon carbide layer by etching using the patterned mask layer as a mask. A gate insulating film is formed on the side wall of the gate trench. A gate electrode is formed on the gate insulating film. The silicon carbide layer has one of hexagonal and cubic crystal types, and the side wall of the gate trench substantially includes one of a{0-33-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.
摘要翻译：通过沉积方法在碳化硅层上形成掩模层。掩模层被图案化。通过使用图案化掩模层作为掩模的蚀刻去除碳化硅层的一部分来形成具有侧壁的栅极沟槽。栅极绝缘膜形成在栅极沟槽的侧壁上。在栅极绝缘膜上形成栅电极。碳化硅层具有六方晶体和立方晶体中的一种，栅极沟槽的侧壁基本上包括{0-33-8}面和{01-1-4}面之一，在硅碳化物层为六方晶系，并且在碳化硅层为立方晶型的情况下，基本上包含{100}面。

10. 发明申请

US20120326166A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120326166A1
公开(公告)日：2012-12-27
申请号：US13529602
申请日：2012-06-21
申请人： Takeyoshi Masuda , Shin Harada , Keiji Wada , Toru Hiyoshi
发明人： Takeyoshi Masuda , Shin Harada , Keiji Wada , Toru Hiyoshi
IPC分类号： H01L29/24 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/049 , H01L21/3065 , H01L29/045 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7395 , H01L29/7397 , H01L29/7813
摘要： A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film.
摘要翻译：衬底具有由具有多晶型4H的六方晶单晶结构的半导体制成的表面。基板的表面通过交替地提供具有（0-33-8）的平面取向的第一平面和连接到第一平面并具有不同于第一平面的平面取向的平面取向的第二平面来构造。栅极绝缘膜设置在基板的表面上。在栅极绝缘膜上设置栅电极。

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