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    • 1. 发明申请
    • SEMICONDUCTOR DEVICE AND LAYOUT DESIGN METHOD FOR THE SAME
    • 半导体器件及其布局设计方法
    • US20110272815A1
    • 2011-11-10
    • US13013442
    • 2011-01-25
    • Akio MisakaYasuko TabataHideyuki AraiTakayuki Yamada
    • Akio MisakaYasuko TabataHideyuki AraiTakayuki Yamada
    • H01L23/528G06F17/50
    • H01L23/528G06F17/50G06F17/5072G06F2217/12H01L23/522H01L2924/0002Y02P90/265H01L2924/00
    • A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features.
    • 半导体器件包括:多个线特征,包括至少一个实际特征,其包括栅电极部分和至少一个虚拟特征。 两个虚拟特征中的两个,并且插入在两个虚拟特征之间并且包括至少一个真实特征的线特征中的至少一个形成均匀间隔的并行运行线特征。 平行运行线特征具有相同的宽度,并行运行线特征的线端部分基本齐平。 线端部均匀化虚拟特征形成在平行运行线特征的线端部的延伸部上。 线端部均匀化虚拟特征包括多个线性特征,每个线性特征具有与每个线特征相同的宽度,并以等于每对相邻线特征之间的间隔的间隔间隔开。
    • 2. 发明授权
    • Semiconductor device and layout design method for the same
    • 半导体器件和布局设计方法相同
    • US08392856B2
    • 2013-03-05
    • US13013442
    • 2011-01-25
    • Akio MisakaYasuko TabataHideyuki AraiTakayuki Yamada
    • Akio MisakaYasuko TabataHideyuki AraiTakayuki Yamada
    • G06F17/50
    • H01L23/528G06F17/50G06F17/5072G06F2217/12H01L23/522H01L2924/0002Y02P90/265H01L2924/00
    • A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features.
    • 半导体器件包括:多个线特征,包括至少一个实际特征,其包括栅电极部分和至少一个虚拟特征。 两个虚拟特征中的两个,并且插入在两个虚拟特征之间并且包括至少一个真实特征的线特征中的至少一个形成均匀间隔的并行运行线特征。 平行运行线特征具有相同的宽度,并行运行线特征的线端部分基本齐平。 线端部均匀化虚拟特征形成在平行运行线特征的线端部的延伸部上。 线端部均匀化虚拟特征包括多个线性特征,每个线性特征具有与每个线特征相同的宽度,并以等于每对相邻线特征之间的间隔间隔。
    • 3. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    • 半导体器件及其制造方法
    • US20110169100A1
    • 2011-07-14
    • US13005085
    • 2011-01-12
    • Hiroji SHIMIZUYoshihiro SatoHideyuki AraiTakayuki YamadaTsutomu Oosuka
    • Hiroji SHIMIZUYoshihiro SatoHideyuki AraiTakayuki YamadaTsutomu Oosuka
    • H01L29/78H01L21/4763
    • H01L27/0629H01L28/20
    • A semiconductor device includes: a first MIS transistor of a first conductivity type having a first active region as a region of a semiconductor substrate surrounded by an element isolation region formed in an upper portion of the semiconductor substrate, a first gate insulating film having a first high dielectric film formed on the first active region, and a first gate electrode formed on the first gate insulating film; and a resistance element having a second high dielectric film formed on the element isolation region and a resistance layer made of silicon formed on the second high dielectric film. The first high dielectric film and the second high dielectric film include the same high dielectric material, and the first high dielectric film includes a first adjustment metal, but the second high dielectric film does not include the first adjustment metal.
    • 一种半导体器件包括:第一导电类型的第一MIS晶体管,具有作为由半导体衬底的上部形成的元件隔离区围绕的半导体衬底的区域的第一有源区,第一栅绝缘膜, 形成在第一有源区上的高电介质膜和形成在第一栅极绝缘膜上的第一栅电极; 以及电阻元件,其具有形成在元件隔离区域上的第二高电介质膜和形成在第二高介电膜上的由硅制成的电阻层。 第一高介电膜和第二高电介质膜包括相同的高介电材料,第一高电介质膜包括第一调节金属,但第二高电介质膜不包括第一调节金属。
    • 4. 发明授权
    • Semiconductor device having gate insulating film including high dielectric material
    • 具有包括高电介质材料的栅极绝缘膜的半导体器件
    • US08558321B2
    • 2013-10-15
    • US13005085
    • 2011-01-12
    • Hiroji ShimizuYoshihiro SatoHideyuki AraiTakayuki YamadaTsutomu Oosuka
    • Hiroji ShimizuYoshihiro SatoHideyuki AraiTakayuki YamadaTsutomu Oosuka
    • H01L21/40
    • H01L27/0629H01L28/20
    • A semiconductor device includes: a first MIS transistor of a first conductivity type having a first active region as a region of a semiconductor substrate surrounded by an element isolation region formed in an upper portion of the semiconductor substrate, a first gate insulating film having a first high dielectric film formed on the first active region, and a first gate electrode formed on the first gate insulating film; and a resistance element having a second high dielectric film formed on the element isolation region and a resistance layer made of silicon formed on the second high dielectric film. The first high dielectric film and the second high dielectric film include the same high dielectric material, and the first high dielectric film includes a first adjustment metal, but the second high dielectric film does not include the first adjustment metal.
    • 一种半导体器件包括:第一导电类型的第一MIS晶体管,具有作为由半导体衬底的上部形成的元件隔离区围绕的半导体衬底的区域的第一有源区,第一栅绝缘膜, 形成在第一有源区上的高电介质膜和形成在第一栅极绝缘膜上的第一栅电极; 以及电阻元件,其具有形成在元件隔离区域上的第二高电介质膜和形成在第二高介电膜上的由硅制成的电阻层。 第一高介电膜和第二高电介质膜包括相同的高介电材料,第一高电介质膜包括第一调节金属,但第二高电介质膜不包括第一调节金属。
    • 5. 发明授权
    • Activated carbon and use therefor
    • 活性炭用于此
    • US09359390B2
    • 2016-06-07
    • US13637250
    • 2011-03-24
    • Mitsunori HitomiTakayuki YoshikawaTakayuki Yamada
    • Mitsunori HitomiTakayuki YoshikawaTakayuki Yamada
    • C07F9/38B01J21/18C01B31/08B01J35/00
    • C07F9/3813B01J21/18B01J35/002C01B32/30C07F9/3808
    • An activated carbon having a high catalytic activity as an oxidation catalyst or a decomposition catalyst, and use therefor are provided.The activated carbon has (a) an oxygen content in a range from 1.40 to 4.30% by mass, (b) a nitrogen content in a range from 0.90 to 2.30% by mass, (c) a sulfur content in a range from 0.50 to 1.20% by mass, and (d) a hydrogen content in a range from 0.40 to 0.65% by mass. The activated carbon may have at least one characteristic of (e) an amount of an acidic surface functional group of 0.10 to 0.36 meq/g, (f) an amount of a basic surface functional group of 0.50 to 1.30 meq/g, and (g) a benzene adsorption capacity of 25 to 50%. The activated carbon catalyzes an oxidation reaction of N-(phosphonomethyl)iminodiacetic acid with a peroxide (e.g., hydrogen peroxide) and achieves an efficient production of N-(phosphonomethyl)glycine even after repetitive use. The activated carbon also efficiently decomposes a chloramine.
    • 提供了作为氧化催化剂或分解催化剂具有高催化活性的活性炭及其用途。 活性炭具有(a)1.40〜4.30质量%的氧含量,(b)氮含量在0.90〜2.30质量%的范围内,(c)硫含量在0.50〜 1.20质量%,(d)氢含量在0.40〜0.65质量%的范围内。 活性炭可以具有以下特征:(e)酸性表面官能团的量为0.10〜0.36meq / g,(f)碱性表面官能团的量为0.50〜1.30meq / g,( g)苯吸附量为25〜50%。 活性炭催化N-(膦酰基甲基)亚氨基二乙酸与过氧化物(例如过氧化氢)的氧化反应,甚至在重复使用后即可有效生产N-(膦酰基甲基)甘氨酸。 活性炭也有效地分解氯胺。
    • 10. 发明授权
    • Semiconductor device and method for manufacturing the same
    • 半导体装置及其制造方法
    • US08476680B2
    • 2013-07-02
    • US13029556
    • 2011-02-17
    • Takayuki Yamada
    • Takayuki Yamada
    • H01L29/76
    • H01L21/76897H01L29/665H01L29/6653H01L29/6656
    • A semiconductor device includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween; a side wall spacer formed on a side wall of the gate electrode; source/drain regions formed in opposing portions of the semiconductor substrate with the gate electrode and the side wall spacer interposed therebetween; and a stress-applying insulating film covering the gate electrode, the side wall spacer, and an upper surface of the semiconductor substrate. A gate-length-direction thickness of an upper portion of the side wall spacer is at least larger than a gate-length-direction thickness of a middle portion thereof.
    • 半导体器件包括:半导体衬底; 形成在半导体衬底上的栅电极,其间插入有栅极绝缘膜; 形成在所述栅电极的侧壁上的侧壁间隔物; 源极/漏极区域形成在半导体衬底的相对部分中,栅电极和侧壁间隔物插入其间; 以及覆盖所述栅电极,所述侧壁间隔物和所述半导体衬底的上表面的应力施加绝缘膜。 侧壁间隔件的上部的栅长方向厚度至少大于其中间部分的栅极长度方向厚度。