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    • 4. 发明授权
    • Charge pump circuit and PLL circuit using same
    • 电荷泵电路和PLL电路使用相同
    • US06960949B2
    • 2005-11-01
    • US11085537
    • 2005-03-22
    • Norihito Suzuki
    • Norihito Suzuki
    • H03L7/093H03L7/089H03L7/095H03L7/06
    • H03L7/0891H03L7/095
    • A charge pump circuit able to enhance the rising and falling characteristics of a current output, drive the current output with a short pulse, reduce leakage current at the OFF time when a current is not output, and realize a reduction of a power consumption and a PLL circuit using same. By outputting a charge current or a discharge current in accordance with an up signal or a down signal and turning on a third transistor (PC, NC) at the OFF time when the current is not output, an inverse bias voltage is supplied between a gate and a source of the second transistor (PA, NA), whereby a reduction of the leakage current can be realized. When the second or third transistor is switched in accordance with the up signal or the down signal, the timing of the control signal is appropriately controlled, simultaneous turning on of the second and third transistors can be avoided, release or injection of charges from and to the output terminal of the charge pump circuit can be prevented, and the stability of an oscillation frequency of a VCO can be improved.
    • 一种能够增强电流输出的上升和下降特性的电荷泵电路,以短脉冲驱动电流输出,在不输出电流时在OFF时减少漏电流,实现功耗的降低和 PLL电路使用相同。 通过根据上升信号或下降信号输出充电电流或放电电流,并且在不输出电流时在OFF时间导通第三晶体管(PC,NC),在栅极之间提供反向偏置电压 和第二晶体管(PA,NA)的源极,从而可以实现漏电流的减小。 当根据上升信号或下降信号切换第二或第三晶体管时,适当地控制控制信号的定时,可以避免第二和第三晶体管的同时导通,从而向第 可以防止电荷泵电路的输出端子,并且可以提高VCO的振荡频率的稳定性。
    • 9. 发明授权
    • Signal multiplexing circuit
    • 信号复用电路
    • US06385214B1
    • 2002-05-07
    • US09231631
    • 1999-01-15
    • Hidekazu KikuchiNorihito Suzuki
    • Hidekazu KikuchiNorihito Suzuki
    • H04K1762
    • H03K17/162H03K17/693
    • A signal multiplexing circuit capable of reducing jitter provided with a first circuit for outputting input differential data by receiving a select drive signal comprising first and second NMOS transistors whose sources are commonly connected, a second circuit for outputting the input differential data with an inverted phase with respect to the output of the first circuit so as to add it to the output of the first circuit and never being selected by a select drive signal comprising third and fourth transistors whose sources are commonly connected, and a signal extracting circuit configured by connecting a connecting point of the sources of the first and second transistors to an output line of a select drive signal of a selector. As a result, jitter of the output signal can be reduced.
    • 一种信号复用电路,其能够减少提供有第一电路的抖动,用于通过接收包括源极共同连接的第一和第二NMOS晶体管的选择驱动信号来输出输入差分数据;第二电路,用于输出具有反相的输入差分数据, 相对于第一电路的输出,以将其添加到第一电路的输出,并且不被包括源极共同连接的第三和第四晶体管的选择驱动信号选择,以及信号提取电路,通过连接 第一和第二晶体管的源极点到选择器的选择驱动信号的输出线。 结果,可以减小输出信号的抖动。