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    • 4. 发明授权
    • Frequency adjustment circuit
    • 频率调节电路
    • US07199676B2
    • 2007-04-03
    • US11196512
    • 2005-08-04
    • Tetsuya TokunagaHiroyuki AraiTakeshi KimuraRyouichi AndoMamoru Yamaguchi
    • Tetsuya TokunagaHiroyuki AraiTakeshi KimuraRyouichi AndoMamoru Yamaguchi
    • H03K3/02
    • H03K3/0231H03K2005/00084
    • A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZP1 and ZP2 generated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.
    • 提供即使在由于外部噪声而使切换电路的频率调整数据变化的情况下也能够维持目标频率的频率调整电路。 频率调整电路包括复位信号生成电路,频率调整数据锁存电路,其锁存并保持由第一切换电路产生的频率调整数据ZP 1和ZP 2,以及基于锁存时钟ZCLK和锁存器的第二切换电路 时钟生成电路,生成锁存时钟ZCLK。 复位信号产生电路产生与从接口电路产生的使能信号EN的上升同步的周期性复位信号ZRES。 锁存时钟产生电路产生与使能信号EN的下降同步的锁存时钟ZCLK。
    • 6. 发明申请
    • LIQUID CRYSTAL DRIVING CIRCUIT
    • 液晶驱动电路
    • US20130038805A1
    • 2013-02-14
    • US13584397
    • 2012-08-13
    • Norikazu KatagiriTetsuya TokunagaTomoshi YoshidaKensuke GotoMamoru Yamaguchi
    • Norikazu KatagiriTetsuya TokunagaTomoshi YoshidaKensuke GotoMamoru Yamaguchi
    • G02F1/1333G02F1/136
    • G09G3/3655G09G3/04G09G3/3614G09G3/3696G09G2330/025
    • A liquid-crystal-driving circuit includes: resistors connected in series between first and second potentials lower than the first potential; one or more voltage follower circuits to impedance-convert one or more intermediate potentials between the first and second potentials, to be outputted, respectively, the intermediate potentials generated at one or more connection points between the resistors, respectively; a common-signal-output circuit to supply common signals to common electrodes of a liquid crystal panel, respectively, the common signals being at the first, second, or one or more intermediate potentials in a predetermined order; and a segment-signal output circuit supplies segment signals to segment electrodes of the liquid crystal panel, respectively, the segment signals being at the first and second potentials, or the intermediate potentials according to the common signals, wherein the segment-signal output circuit increases impedances of the segment signals only for a first period when the of segment signals potentials are switched.
    • 液晶驱动电路包括:电阻器,其串联连接在低于第一电位的第一和第二电位之间; 一个或多个电压跟随器电路,用于阻抗转换第一和第二电位之间的一个或多个中间电位,分别输出在电阻器之间的一个或多个连接点产生的中间电位; 公共信号输出电路,分别向液晶面板的公共电极提供公共信号,共同信号处于第一,第二或一个或多个中间电位,以预定顺序; 分段信号输出电路分别将分段信号提供给液晶面板的分段电极,根据公共信号分段信号处于第一和第二电位或中间电位,其中分段信号输出电路增加 段信号的阻抗仅在片段信号电位切换时的第一周期。
    • 7. 发明申请
    • Frequency adjustment circuit
    • 频率调节电路
    • US20060033583A1
    • 2006-02-16
    • US11196512
    • 2005-08-04
    • Tetsuya TokunagaHiroyuki AraiTakeshi KimuraRyouichi AndoMamoru Yamaguchi
    • Tetsuya TokunagaHiroyuki AraiTakeshi KimuraRyouichi AndoMamoru Yamaguchi
    • H03L7/00
    • H03K3/0231H03K2005/00084
    • A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZP1 and ZP2 generated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.
    • 提供即使在由于外部噪声而使切换电路的频率调整数据变化的情况下也能够维持目标频率的频率调整电路。 频率调整电路包括复位信号生成电路,频率调整数据锁存电路,其锁存并保持由第一切换电路产生的频率调整数据ZP 1和ZP 2,以及基于锁存时钟ZCLK和锁存器的第二切换电路 时钟生成电路,生成锁存时钟ZCLK。 复位信号产生电路产生与从接口电路产生的使能信号EN的上升同步的周期性复位信号ZRES。 锁存时钟产生电路产生与使能信号EN的下降同步的锁存时钟ZCLK。
    • 8. 发明授权
    • Domestic satellite communication system
    • 国内卫星通信系统
    • US4616108A
    • 1986-10-07
    • US636844
    • 1984-08-01
    • Mamoru YamaguchiMasanori Oshima
    • Mamoru YamaguchiMasanori Oshima
    • H04B7/15H04B17/00H04B17/309H04Q3/00H01M11/00
    • H04Q3/0016
    • A direct broadcast communication satellite system prevents over-charge for earth-subscriber to earth-subscriber toll calls via radio links to an earth station regardless of faults which may occur in satellite channels. A central earth station controls the frequency assignment of the radio link channels used for voice communication. Each of a plurality of subscriber earth stations has at least one voice communication terminal, with means for identifying a call destined for a subscriber at that earth station. The continuity of the channels involved in that call are monitored by periodically transmitting and receiving out-of-band signals on the assigned channel. It appears that there has been a loss of signal when the out-of-band signal does not appear, twice in succession. Then, the channel is released and the toll charges are terminated.
    • 直接广播通信卫星系统防止地球用户通过无线电链路到地球站的地面用户长途电话的过量充电,而不管卫星信道中可能发生的故障。 中央地球站控制用于语音通信的无线电链路信道的频率分配。 多个用户地球站中的每一个具有至少一个语音通信终端,具有用于识别发往该地球站上的用户的呼叫的装置。 通过在分配的信道周期性地发送和接收带外信号来监视涉及该呼叫的信道的连续性。 当带外信号不出现时,连续两次出现信号丢失。 然后,通道被释放,并且终止费用。