专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07105070B2 Method for producing ceramic substrate, and ceramic substrate 有权
标题翻译：陶瓷基板和陶瓷基板的制造方法
公开(公告)号：US07105070B2
公开(公告)日：2006-09-12
申请号：US10935164
申请日：2004-09-08
申请人： Akifumi Tosa , Jun Otsuka , Manabu Sato , Hisahito Kashima
发明人： Akifumi Tosa , Jun Otsuka , Manabu Sato , Hisahito Kashima
IPC分类号： B32B37/06 , B32B38/10 , C03B29/00 , H05K3/26 , H05K3/46
CPC分类号： B32B18/00 , C03C14/004 , C03C2214/20 , C04B2235/6567 , C04B2235/9615 , C04B2237/341 , C04B2237/343 , C04B2237/346 , C04B2237/56 , C04B2237/562 , C04B2237/565 , C04B2237/568 , C04B2237/66 , C04B2237/68 , C04B2237/702 , C04B2237/704 , H01G4/30 , H01L21/481 , H01L21/4857 , H05K1/0306 , H05K3/246 , H05K3/4611 , H05K3/4629 , H05K2201/0347 , H05K2201/09881 , H05K2203/308
摘要： A method for producing a ceramic substrate which employs a cofiring process using restraint sheets in which a second ceramic green sheet 7 is laminated on a green ceramic substrate 30 so as to cover surface conductors 32 of the green ceramic substrate 30, the second ceramic green sheet 7 subsequently being integrated with the green ceramic substrate 30. Restraint sheets 9, which are not sintered at a sintering temperature at which the green ceramic substrate 30 is sintered, are laminated on corresponding opposite sides of the green ceramic substrate 30 so as to restrain the green ceramic substrate 30 together with the second ceramic green sheet 7. The second ceramic green sheet 7 and the green ceramic substrate 30 are fired at a temperature at which the second ceramic green sheet 7 and the green ceramic substrate 30 are integrally sintered, whereas the restraint sheets 9 are not sintered, to thereby yield a ceramic substrate 40. The restraint sheets 9 and a ceramic covering layer 7a which covers the surface conductors 32 are removed, to thereby expose the surface conductor layer 32. A plating layer 31 is formed on the surface conductor layer 32.
摘要翻译：一种陶瓷基板的制造方法，其使用使用在生陶瓷基板30上层叠有第二陶瓷生片7以将陶瓷基板30的表面导体32覆盖的第二陶瓷生片的约束片， 7随后与绿色陶瓷基板30集成。在烧结生坯陶瓷基板30的烧结温度下没有烧结的约束片9层叠在生陶瓷基板30的对应的相对侧，以便与第二陶瓷生片一起抑制生陶瓷基板30 7。第二陶瓷生片7和生陶瓷基片30在第二陶瓷生片7和生陶瓷基片30一体烧结的温度下烧制，而约束片9不烧结，从而产生陶瓷基片 40。去除约束片9和覆盖表面导体32的陶瓷覆盖层7a，从而露出表面导体层32。在表面导体层32上形成镀层31。

2. 发明申请

US20050051253A1 Method for producing ceramic substrate, and ceramic substrate 有权
标题翻译：陶瓷基板和陶瓷基板的制造方法
公开(公告)号：US20050051253A1
公开(公告)日：2005-03-10
申请号：US10935164
申请日：2004-09-08
申请人： Akifumi Tosa , Jun Otsuka , Manabu Sato , Hisahito Kashima
发明人： Akifumi Tosa , Jun Otsuka , Manabu Sato , Hisahito Kashima
IPC分类号： H01G4/12 , B32B18/00 , C03C14/00 , H01G4/005 , H01G4/30 , H01L21/48 , H05K1/03 , H05K3/24 , H05K3/46 , C03B29/00
CPC分类号： B32B18/00 , C03C14/004 , C03C2214/20 , C04B2235/6567 , C04B2235/9615 , C04B2237/341 , C04B2237/343 , C04B2237/346 , C04B2237/56 , C04B2237/562 , C04B2237/565 , C04B2237/568 , C04B2237/66 , C04B2237/68 , C04B2237/702 , C04B2237/704 , H01G4/30 , H01L21/481 , H01L21/4857 , H05K1/0306 , H05K3/246 , H05K3/4611 , H05K3/4629 , H05K2201/0347 , H05K2201/09881 , H05K2203/308
摘要： A method for producing a ceramic substrate which employs a cofiring process using restraint sheets in which a second ceramic green sheet 7 is laminated on a green ceramic substrate 30 so as to cover surface conductors 32 of the green ceramic substrate 30, the second ceramic green sheet 7 subsequently being integrated with the green ceramic substrate 30. Restraint sheets 9, which are not sintered at a sintering temperature at which the green ceramic substrate 30 is sintered, are laminated on corresponding opposite sides of the green ceramic substrate 30 so as to restrain the green ceramic substrate 30 together with the second ceramic green sheet 7. The second ceramic green sheet 7 and the green ceramic substrate 30 are fired at a temperature at which the second ceramic green sheet 7 and the green ceramic substrate 30 are integrally sintered, whereas the restraint sheets 9 are not sintered, to thereby yield a ceramic substrate 40. The restraint sheets 9 and a ceramic covering layer 7a which covers the surface conductors 32 are removed, to thereby expose the surface conductor layer 32. A plating layer 31 is formed on the surface conductor layer 32.
摘要翻译：一种陶瓷基板的制造方法，其使用使用在生陶瓷基板30上层叠有第二陶瓷生片7以将陶瓷基板30的表面导体32覆盖的第二陶瓷生片的约束片，随后与绿色陶瓷基板30一体化。在烧结生坯陶瓷基板30的烧结温度下未烧结的约束片9层叠在生陶瓷基板30的相应的相对侧上，以便限制绿色陶瓷基板30与第二陶瓷生片7.第二陶瓷生片7和生陶瓷基片30在第二陶瓷生片7和生陶瓷基片30一体烧结的温度下烧制，而约束片9不被烧结，从而产生陶瓷基片40.约束片9和陶瓷覆盖层7a 覆盖表面导体32，从而露出表面导体层32.镀层31形成在表面导体层32上。

3. 发明授权

US07072169B2 Capacitor and method for manufacturing the same 失效
标题翻译：电容器及其制造方法
公开(公告)号：US07072169B2
公开(公告)日：2006-07-04
申请号：US11003767
申请日：2004-12-06
申请人： Kazuhiro Hayashi , Akifumi Tosa , Motohiko Sato , Jun Otsuka , Manabu Sato
发明人： Kazuhiro Hayashi , Akifumi Tosa , Motohiko Sato , Jun Otsuka , Manabu Sato
IPC分类号： H01G4/228
CPC分类号： H01G4/30 , H01G4/12
摘要： A laminated ceramic capacitor 10 divided into a first laminate 11, a second laminate 12, a third laminate 13, and a fourth laminate 14. The first laminate 11 includes a ceramic layer 15 serving as a dielectric layer. The ceramic layer 15 is thicker than a ceramic layer 17 sandwiched between internal electrodes 16a in the second laminate 12 or the fourth laminate 14, and thinner than 20 times the thickness of the ceramic layer 17. The third laminate 13 includes dielectric layers, which serve as the ceramic layers 17, and has a thickness of 5% of the total thickness of the second laminate 12 and the fourth laminate 14. Accordingly, the third laminate 13 achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate 11, portions of via electrodes 18 that extend without being electrically connected to the internal electrodes 16b can be shortened.
摘要翻译：层叠陶瓷电容器10分为第一层压体11，第二层压体12，第三层压体13和第四层压体14.第一层压体11包括用作电介质层的陶瓷层15。陶瓷层15比夹在第二层叠体12或第四层叠体14的内部电极16a之间的陶瓷层17厚，比陶瓷层17的厚度薄20倍以上。第三层叠体13包括电介质层，用作陶瓷层17，并且具有第二层压体12和第四层压体14的总厚度的5％的厚度。因此，第三层压体13具有吸收电极引起的厚度差的功能。此外，通过调节第一层压体11的厚度，可以缩短延伸而不与内部电极16b电连接的通孔电极18的部分。

4. 发明申请

US20050122662A1 Capacitor and method for manufacturing the same 失效
标题翻译：电容器及其制造方法
公开(公告)号：US20050122662A1
公开(公告)日：2005-06-09
申请号：US11003767
申请日：2004-12-06
申请人： Kazuhiro Hayashi , Akifumi Tosa , Motohiko Sato , Jun Otsuka , Manabu Sato
发明人： Kazuhiro Hayashi , Akifumi Tosa , Motohiko Sato , Jun Otsuka , Manabu Sato
IPC分类号： H01G4/12 , H01G4/30 , H01G4/06
CPC分类号： H01G4/30 , H01G4/12
摘要： A laminated ceramic capacitor 10 divided into a first laminate 11, a second laminate 12, a third laminate 13, and a fourth laminate 14. The first laminate 11 includes a ceramic layer 15 serving as a dielectric layer. The ceramic layer 15 is thicker than a ceramic layer 17 sandwiched between internal electrodes 16a in the second laminate 12 or the fourth laminate 14, and thinner than 20 times the thickness of the ceramic layer 17. The third laminate 13 includes dielectric layers, which serve as the ceramic layers 17, and has a thickness of 5% of the total thickness of the second laminate 12 and the fourth laminate 14. Accordingly, the third laminate 13 achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate 11, portions of via electrodes 18 that extend without being electrically connected to the internal electrodes 16b can be shortened.
摘要翻译：层叠陶瓷电容器10分为第一层压体11，第二层压体12，第三层压体13和第四层压体14.第一层压体11包括用作电介质层的陶瓷层15。陶瓷层15比夹在第二层叠体12或第四层叠体14的内部电极16a之间的陶瓷层17厚，比陶瓷层17的厚度薄20倍以上。第三层叠体13包括电介质层，用作陶瓷层17，并且具有第二层压体12和第四层压体14的总厚度的5％的厚度。因此，第三层压体13具有吸收电极引起的厚度差的功能。此外，通过调节第一层压体11的厚度，可以缩短延伸而不与内部电极16b电连接的通孔电极18的部分。

5. 发明授权

US07233480B2 Capacitor and method for manufacturing the same 有权
标题翻译：电容器及其制造方法
公开(公告)号：US07233480B2
公开(公告)日：2007-06-19
申请号：US11475891
申请日：2006-06-28
申请人： Kazuhiro Hayashi , Akifumi Tosa , Motohiko Sato , Jun Otsuka , Manabu Sato
发明人： Kazuhiro Hayashi , Akifumi Tosa , Motohiko Sato , Jun Otsuka , Manabu Sato
IPC分类号： H01G4/228
CPC分类号： H01G4/30 , H01G4/12
摘要： A laminated ceramic capacitor (10) divided into a first laminate (11), a second laminate (12), a third laminate (13), and a fourth laminate (14). The first laminate (11) includes a ceramic layer (15) serving as a dielectric layer. The ceramic layer (15) is thicker than a ceramic layer (17) sandwiched between internal electrodes (16a) in the second laminate (12) or the fourth laminate (14), and thinner than 20 times the thickness of the ceramic layer (17). The third laminate (13) includes dielectric layers, which serve as the ceramic layers (17), and has a thickness of 5% of the total thickness of the second laminate (12) and the fourth laminate (14). Accordingly, the third laminate (13) achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate (11), portions of via electrodes (18) that extend without being electrically connected to the internal electrodes (16b) can be shortened.
摘要翻译：分为第一层压体（11），第二层压板（12），第三层压板（13）和第四层压板（14）的层压陶瓷电容器（10）。第一层压体（11）包括用作电介质层的陶瓷层（15）。陶瓷层（15）比夹在第二层叠体（12）或第四层叠体（14）的内部电极（16a）之间的陶瓷层（17）厚，比陶瓷层（15）的厚度薄 17）。第三层压体（13）包括作为陶瓷层（17）的电介质层，其厚度为第二层叠体（12）和第四层叠体（14）的总厚度的5％。因此，第三层压体（13）实现吸收电极引起的厚度差的功能。此外，通过调整第一层压体（11）的厚度，能够缩短在不与内部电极（16b）电连接的情况下延伸的通孔电极（18）的部分。

6. 发明申请

US20060245142A1 Capacitor and method for manufacturing the same 有权
标题翻译：电容器及其制造方法
公开(公告)号：US20060245142A1
公开(公告)日：2006-11-02
申请号：US11475891
申请日：2006-06-28
申请人： Kazuhiro Hayashi , Akifumi Tosa , Motohiko Sato , Jun Otsuka , Manabu Sato
发明人： Kazuhiro Hayashi , Akifumi Tosa , Motohiko Sato , Jun Otsuka , Manabu Sato
IPC分类号： H01G4/228
CPC分类号： H01G4/30 , H01G4/12
摘要： A laminated ceramic capacitor (10) divided into a first laminate (11), a second laminate (12), a third laminate (13), and a fourth laminate (14). The first laminate (11) includes a ceramic layer (15) serving as a dielectric layer. The ceramic layer (15) is thicker than a ceramic layer (17) sandwiched between internal electrodes (16a) in the second laminate (12) or the fourth laminate (14), and thinner than 20 times the thickness of the ceramic layer (17). The third laminate (13) includes dielectric layers, which serve as the ceramic layers (17), and has a thickness of 5% of the total thickness of the second laminate (12) and the fourth laminate (14). Accordingly, the third laminate (13) achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate (11), portions of via electrodes (18) that extend without being electrically connected to the internal electrodes (16b) can be shortened.
摘要翻译：分为第一层压体（11），第二层压板（12），第三层压板（13）和第四层压板（14）的层压陶瓷电容器（10）。第一层压体（11）包括用作电介质层的陶瓷层（15）。陶瓷层（15）比夹在第二层叠体（12）或第四层叠体（14）的内部电极（16a）之间的陶瓷层（17）厚，比陶瓷层（15）的厚度薄 17）。第三层压体（13）包括作为陶瓷层（17）的电介质层，其厚度为第二层叠体（12）和第四层叠体（14）的总厚度的5％。因此，第三层压体（13）实现吸收电极引起的厚度差的功能。此外，通过调整第一层压体（11）的厚度，能够缩短在不与内部电极（16b）电连接的情况下延伸的通孔电极（18）的部分。

7. 发明授权

US06844284B2 Dielectric porcelain composition 失效
标题翻译：介电瓷组成
公开(公告)号：US06844284B2
公开(公告)日：2005-01-18
申请号：US10291647
申请日：2002-11-12
申请人： Akifumi Tosa , Jun Otsuka , Manabu Sato
发明人： Akifumi Tosa , Jun Otsuka , Manabu Sato
IPC分类号： C04B35/00 , C04B35/01 , C04B35/46 , C04B35/462 , C04B35/475 , H01B3/12 , H01P1/205 , H01P7/10 , C04B35/468
CPC分类号： C04B35/475 , C04B35/462 , C04B35/62695 , C04B2235/3201 , C04B2235/3215 , C04B2235/3224 , C04B2235/3298 , C04B2235/604 , C04B2235/94 , H01P1/2056
摘要： A dielectric porcelain composition comprising Ba, Nd, Pr, Bi, Ti and at least one of Na and K and satisfying a condition that when the composition is expressed by composition formula: BaO—aNdO3/2—bPrO11/6—cBiO3/2—dTiO2—eAO1/2, wherein A is at least one of Na and K, and a, b, c, d and e represent a molar ratio, a, b, c, d and e are in respective ranges of 1.5≦a≦2.6, 0.02≦b≦1.00, 0.2≦c≦0.6, 4.5≦d≦5.5 and 0.02≦e≦0.30.
摘要翻译：包含Ba，Nd，Pr，Bi，Ti和Na和K中的至少一种的电介质瓷组合物，并且满足以下条件：当组合物由组成式表示时：BaO-aNdO3 / 2-bPrO11 / 6-cBiO3 / 2- dTiO 2 -eAO1 / 2，其中A是Na和K中的至少一种，a，b，c，d和e表示摩尔比a，b，c，d和e分别在1.5 <= a <= 2.6,0.02 <= b <= 1.00,0.2 <= c <= 0.6,4.5 <= d <= 5.5和0.02 <= E＆LE; 0.30。

8. 发明授权

US08697534B2 Capacitor to be incorporated in wiring substrate, method for manufacturing the capacitor, and wiring substrate 有权
标题翻译：配线基板中的电容器，电容器的制造方法以及布线基板
公开(公告)号：US08697534B2
公开(公告)日：2014-04-15
申请号：US13610936
申请日：2012-09-12
申请人： Motohiko Sato , Kazuhiro Hayashi , Kenji Murakami , Motonobu Kurahashi , Yusuke Kaieda , Jun Otsuka , Manabu Sato
发明人： Motohiko Sato , Kazuhiro Hayashi , Kenji Murakami , Motonobu Kurahashi , Yusuke Kaieda , Jun Otsuka , Manabu Sato
IPC分类号： H01L21/20
CPC分类号： H05K1/0231 , H01G4/228 , H01G4/30 , H01G4/38 , H01L23/49822 , H01L2924/0002 , H01L2924/3511 , H05K1/185 , H05K3/4602 , H05K2201/10712 , H01L2924/00
摘要： A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.
摘要翻译：一种电容器，其具有电容器，所述电容器包括：电容器主体，包括多个电介质层和设置在所述不同电介质层之间的内部电极层，其中所述电容器本体在所述电容器主体的至少一个侧面中，从所述电容器主体的第一主面和位于与所述第一主面相反的一侧的第二主面中的至少一个在所述电容器本体的厚度方向上延伸的凹部。

9. 发明授权

US07473988B2 Wiring board construction including embedded ceramic capacitors(s) 有权
标题翻译：接线板结构包括嵌入式陶瓷电容器
公开(公告)号：US07473988B2
公开(公告)日：2009-01-06
申请号：US11513249
申请日：2006-08-31
申请人： Kazuhiro Urashima , Shinji Yuri , Manabu Sato , Jun Otsuka
发明人： Kazuhiro Urashima , Shinji Yuri , Manabu Sato , Jun Otsuka
IPC分类号： H01L23/495
CPC分类号： H05K1/185 , H01G2/06 , H01G4/38 , H01L21/568 , H01L21/6835 , H01L23/50 , H01L23/5383 , H01L23/5386 , H01L23/642 , H01L24/81 , H01L2221/68345 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16237 , H01L2224/81192 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01042 , H01L2924/01047 , H01L2924/01056 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , H05K1/0231 , H05K3/4602 , H05K2201/10522 , H05K2201/10674 , H05K2201/10712 , H01L2924/00 , H01L2224/05599
摘要： A wiring board includes a substrate core, ceramic capacitors and a built-up layer. The substrate core has a housing opening portion therein which opens at a core main surface. The ceramic capacitors are accommodated in the housing opening portion and oriented such that the core main surface and a capacitor main surface of each capacitor face the same way. The built-up layer includes semiconductor integrated circuit element mounting areas at various locations on a surface thereof. In the substrate core, each ceramic capacitor is respectively disposed in an area corresponding to each semiconductor integrated circuit element mounting area.
摘要翻译：布线板包括基板芯，陶瓷电容器和积层。基板芯具有在芯主表面上开口的壳体开口部分。陶瓷电容器容纳在壳体开口部分中并且取向为使得每个电容器的芯主表面和电容器主表面相同。积层在其表面上的各个位置包括半导体集成电路元件安装区域。在基板芯中，每个陶瓷电容器分别设置在对应于每个半导体集成电路元件安装区域的区域中。

10. 发明授权

US07332231B2 Ceramic substrate for thin film electronic component, production method for the same and thin film electronic component using the same 有权
标题翻译：用于薄膜电子元件的陶瓷基板，使用该薄膜电子元件的薄膜电子元件的制造方法
公开(公告)号：US07332231B2
公开(公告)日：2008-02-19
申请号：US10958569
申请日：2004-10-06
申请人： Seiji Ichiyanagi , Jun Otsuka , Manabu Sato
发明人： Seiji Ichiyanagi , Jun Otsuka , Manabu Sato
IPC分类号： C03C27/00 , B32B5/14
CPC分类号： H01L23/49894 , H01G4/228 , H01G4/33 , H01L29/78603 , H01L2221/68345 , H01L2224/13 , H01L2924/09701 , H01L2924/15311 , H05K1/0306 , H05K1/162 , H05K3/4629 , Y10S428/901 , Y10T428/12604 , Y10T428/24364 , Y10T428/24917 , Y10T428/24926 , Y10T428/249956
摘要： A ceramic substrate for a thin film electronic component, a production method thereof, and a thin film electronic component using the ceramic substrate A first substrate (1) includes a dense glass-ceramic mixed layer (33) containing glass in its surface portion. A second substrate is prepared such that a glass layer (32) formed on a surface of a substrate base portion (2) is subjected to a heat-pressure treatment so as to form or rather partly change the glass portion (32) into a dense glass-ceramic mixed layer (33) in which glass is dispersed into a surface portion of the substrate base portion (2). A surface of the dense glass-ceramic mixed layer (33) is then subjected to grinding or rather polishing to flatten and expose a surface of the dense glass-ceramic mixed layer (32). A third substrate includes a substrate base portion (2) having a dense glass-ceramic mixed layer (33) containing glass on a surface portion in one face side, and a wiring pattern (21) formed inside the substrate base portion (2). In the wiring pattern (21), one end thereof is exposed on or from a surface of the dense glass-ceramic mixed layer (33) and the other end is exposed on or from another surface of the substrate.
摘要翻译：一种薄膜电子部件用陶瓷基板及其制造方法以及使用该陶瓷基板的薄膜电子部件。第一基板（1）在其表面部分包括含有玻璃的致密玻璃 - 陶瓷混合层（33）。制备第二基板，使得形成在基板基部（2）的表面上的玻璃层（32）进行热压处理，以便将玻璃部分（32）形成或相当部分地变成致密的将玻璃分散在基板基部（2）的表面部分的玻璃 - 陶瓷混合层（33）。然后将致密的玻璃 - 陶瓷混合层（33）的表面进行研磨或进行抛光以使致密玻璃 - 陶瓷混合层（32）的表面变平并暴露。第三基板包括在一个正面侧的表面部分上具有含有玻璃的致密玻璃 - 陶瓷混合层（33）的基板基部（2）和形成在基板基部（2）内部的布线图案（21）。在布线图案（21）中，其一端在致密玻璃 - 陶瓷混合层（33）的表面上露出，另一端暴露在基板的另一表面上或从基板的另一表面露出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式