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1. 发明授权

US5328872A Method of integrated circuit manufacturing using deposited oxide 失效
标题翻译：使用沉积氧化物的集成电路制造方法
公开(公告)号：US5328872A
公开(公告)日：1994-07-12
申请号：US459167
申请日：1989-12-29
申请人： Ajit S. Manocha , Virendra V. S. Rana , James F. Roberts , Ankineedu Velaga
发明人： Ajit S. Manocha , Virendra V. S. Rana , James F. Roberts , Ankineedu Velaga
IPC分类号： H01L21/316 , C23C16/40 , C23C16/44 , C23C16/54 , H01L21/31 , H01L21/02
CPC分类号： C23C16/54 , C23C16/401 , C23C16/4412
摘要： Contamination of LPCVDBP TEOS films is reduced by preventing volatile compounds, resulting from reactions of the residue in the outlet of the furnace from reaching the deposition portion of the furnace where they would otherwise react with the deposition gases to produce chemically generated particles which contaminate the dielectric film.
摘要翻译： LPCVDBP TEOS膜的污染通过防止挥发性化合物的降低，这是由于炉子出口处的残余物的反应到达炉的沉积部分，否则它们将与沉积气体反应以产生污染电介质的化学产生的颗粒电影。

2. 发明授权

US5147820A Silicide formation on polysilicon 失效
标题翻译：多晶硅上的硅化物形成
公开(公告)号：US5147820A
公开(公告)日：1992-09-15
申请号：US749762
申请日：1991-08-26
申请人： Sailesh Chittipeddi , Pradip K. Roy , Ankineedu Velaga
发明人： Sailesh Chittipeddi , Pradip K. Roy , Ankineedu Velaga
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L21/28052
摘要： An integrated circuit includes a doped polysilicon/silicide ("polycide") gate electrode. The doped polysilicon layer comprises sub-layers. The sub-layers are formed by varying the silicon deposition conditions, typically including the deposition rate, while decreasing the dopant concentration. The metal silicide layer is then formed on top of the doped polysilicon layer. An improvement in uniformity and planarity of the structure is obtained as a result of stress accommodation. In addition, the sub-layers reduce the channeling effect that occurs during high energy source/drain dopant implantation. These effects allow for a reduced stack height of the gate electrode, resulting in improvements in very small (sub-micron) device structures.

3. 发明授权

US06500729B1 Method for reducing dishing related issues during the formation of shallow trench isolation structures 有权
标题翻译：在形成浅沟槽隔离结构期间减少凹陷相关问题的方法
公开(公告)号：US06500729B1
公开(公告)日：2002-12-31
申请号：US09586384
申请日：2000-06-02
申请人： Sailesh Chittipeddi , Arun Kumar Nanda , Ankineedu Velaga
发明人： Sailesh Chittipeddi , Arun Kumar Nanda , Ankineedu Velaga
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for forming shallow trench isolation structures produces a shallow trench isolation structure having a substantially planar upper surface. The shallow trench isolation structure is formed from an originally formed shallow trench isolation structure which includes a deposited dielectric material within a trench and which exhibits dishing related problems in the form of a void formed within the trench, wherein the surface of the deposited dielectric material is recessed below the planar upper surface. The method provides for filling the void with a silicon film. The silicon film is then polished in its as-deposited or oxidized form, to produce a shallow trench isolation structure having a planar upper surface.
摘要翻译：形成浅沟槽隔离结构的方法产生具有基本平坦的上表面的浅沟槽隔离结构。浅沟槽隔离结构由原始形成的浅沟槽隔离结构形成，其包括在沟槽内的沉积的介电材料，并且其呈现出形成在沟槽内的空隙形式的凹陷相关问题，其中沉积的介电材料的表面是凹进平面上表面下方。该方法提供用硅膜填充空隙。然后以其沉积或氧化形式抛光硅膜，以产生具有平坦上表面的浅沟槽隔离结构。

4. 发明授权

US06358785B1 Method for forming shallow trench isolation structures 有权
标题翻译：形成浅沟槽隔离结构的方法
公开(公告)号：US06358785B1
公开(公告)日：2002-03-19
申请号：US09588058
申请日：2000-06-06
申请人： Sailesh Chittipeddi , Arun Kumar Nanda , Ankineedu Velaga
发明人： Sailesh Chittipeddi , Arun Kumar Nanda , Ankineedu Velaga
IPC分类号： H01L21338
CPC分类号： H01L21/76227
摘要： A method for forming a shallow trench isolation structure within a semiconductor substrate includes forming a trench opening within a semiconductor substrate having an oxidation-resistant material as a top surface. An oxide liner is formed on inner surfaces of the trench opening. A silicon material is then introduced into the trench opening and over the top surface. The silicon material is subsequently oxidized, either before or after a polishing operation is used to planarize the structure. Dishing related problems are avoided during polishing because the silicon or oxidized silicon material has a polishing rate similar to the oxidation resistant material, and less than that of conventionally formed CVD oxides.
摘要翻译：在半导体衬底内形成浅沟槽隔离结构的方法包括在半导体衬底内形成具有抗氧化材料作为顶表面的沟槽开口。氧化物衬垫形成在沟槽开口的内表面上。然后将硅材料引入沟槽开口并在顶表面上。在抛光操作用于平面化结构之前或之后，硅材料随后被氧化。由于硅或氧化硅材料的抛光速率与耐氧化材料相似，并且小于常规形成的CVD氧化物的抛光速率，所以在抛光过程中避免了相关的问题。

5. 发明授权

US06218300B1 Method and apparatus for forming a titanium doped tantalum pentaoxide dielectric layer using CVD 失效
标题翻译：使用CVD形成掺杂钛的五氧化钽电介质层的方法和装置
公开(公告)号：US06218300B1
公开(公告)日：2001-04-17
申请号：US09097301
申请日：1998-06-12
申请人： Pravin K. Narwankar , Turgut Sahin , Randall S. Urdahl , Ankineedu Velaga , Patricia Liu
发明人： Pravin K. Narwankar , Turgut Sahin , Randall S. Urdahl , Ankineedu Velaga , Patricia Liu
IPC分类号： H01L2144
CPC分类号： C23C16/405
摘要： A method and apparatus for forming a titanium doped tantalum pentaoxide dielectric using a CVD process. According to the present invention a substrate is placed in the deposition chamber. A source of tantalum, a source of titanium, and an oxygen containing gas are then fed into the chamber. Thermal energy is used to decompose the source of tantalum to form tantalum atoms, and decompose the source of titanium to form titanium atoms in the deposition chamber. The titanium atoms, tantalum atoms and the oxygen containing gas then react to form a tantalum pentaoxide dielectric film doped with titanium.
摘要翻译：使用CVD工艺形成掺杂钛的五氧化钽电介质的方法和装置。根据本发明，将基板放置在沉积室中。然后将钽源，钛源和含氧气体进料到室中。热能用于分解钽源以形成钽原子，并且在沉积室中分解钛源以形成钛原子。然后，钛原子，钽原子和含氧气体反应形成掺杂有钛的五氧化钽电介质膜。

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