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1. 发明授权

US07790631B2 Selective deposition of a dielectric on a self-assembled monolayer-adsorbed metal 有权
标题翻译：在自组装单层吸附金属上选择性沉积电介质
公开(公告)号：US07790631B2
公开(公告)日：2010-09-07
申请号：US11603522
申请日：2006-11-21
申请人： Ajay K. Sharma , Sean King , Dennis Hanken , Andrew W. Ott
发明人： Ajay K. Sharma , Sean King , Dennis Hanken , Andrew W. Ott
IPC分类号： H01L21/31
CPC分类号： H01L21/0228 , B05D1/185 , B05D7/52 , H01L21/022 , H01L21/28079 , H01L21/31133 , H01L21/31144 , H01L21/3141 , H01L21/76825 , H01L21/76832 , H01L21/76834 , H01L21/76897 , H01L29/495 , H01L29/517 , H01L29/6656 , H01L29/6659
摘要： Methods and apparatuses to selectively deposit a dielectric on a self-assembled monolayer (“SAM”) adsorbed metal are described. A wafer includes a device having a first electrode. A first self-assembled monolayer is deposited on the wafer covering the first electrode. Next, a portion of the first self-assembled monolayer is removed to expose the first electrode. The first self-assembled monolayer includes a hydrophobic layer. Further, second self-assembled monolayer is deposited on the first electrode. The second self-assembled monolayer includes a hydrophilic layer. Next, an insulating layer is deposited on the second self-assembled monolayer. Further, self-aligned contacts to one or more second electrodes of the device are formed.
摘要翻译：描述了在自组装单层（“SAM”）吸附的金属上选择性地沉积电介质的方法和装置。晶片包括具有第一电极的器件。第一自组装单层沉积在覆盖第一电极的晶片上。接下来，去除第一自组装单层的一部分以露出第一电极。第一自组装单层包括疏水层。此外，第二自组装单层沉积在第一电极上。第二自组装单层包括亲水层。接下来，绝缘层沉积在第二自组装单层上。此外，形成了与器件的一个或多个第二电极的自对准接触。

2. 发明申请

US20080116481A1 Selective deposition of a dielectric on a self-assembled monolayer-adsorbed metal 有权
标题翻译：在自组装单层吸附金属上选择性沉积电介质
公开(公告)号：US20080116481A1
公开(公告)日：2008-05-22
申请号：US11603522
申请日：2006-11-21
申请人： Ajay K. Sharma , Sean King , Dennis Hanken , Andrew W. Ott
发明人： Ajay K. Sharma , Sean King , Dennis Hanken , Andrew W. Ott
IPC分类号： B05D5/12 , H01L29/40
CPC分类号： H01L21/0228 , B05D1/185 , B05D7/52 , H01L21/022 , H01L21/28079 , H01L21/31133 , H01L21/31144 , H01L21/3141 , H01L21/76825 , H01L21/76832 , H01L21/76834 , H01L21/76897 , H01L29/495 , H01L29/517 , H01L29/6656 , H01L29/6659
摘要： Methods and apparatuses to selectively deposit a dielectric on a self-assembled monolayer (“SAM”) adsorbed metal are described. A wafer includes a device having a first electrode. A first self-assembled monolayer is deposited on the wafer covering the first electrode. Next, a portion of the first self-assembled monolayer is removed to expose the first electrode. The first self-assembled monolayer includes a hydrophobic layer. Further, second self-assembled monolayer is deposited on the first electrode. The second self-assembled monolayer includes a hydrophilic layer. Next, an insulating layer is deposited on the second self-assembled monolayer. Further, self-aligned contacts to one or more second electrodes of the device are formed.
摘要翻译：描述了在自组装单层（“SAM”）吸附的金属上选择性地沉积电介质的方法和装置。晶片包括具有第一电极的器件。第一自组装单层沉积在覆盖第一电极的晶片上。接下来，去除第一自组装单层的一部分以露出第一电极。第一自组装单层包括疏水层。此外，第二自组装单层沉积在第一电极上。第二自组装单层包括亲水层。接下来，绝缘层沉积在第二自组装单层上。此外，形成了与器件的一个或多个第二电极的自对准接触。

3. 发明授权

US09074684B2 Transmission gear shift indication techniques 有权
标题翻译：变速箱换挡指示技术
公开(公告)号：US09074684B2
公开(公告)日：2015-07-07
申请号：US14034598
申请日：2013-09-24
申请人： Songping Yu , Mohamed Othman , Ryan B McNamara , Sean King
发明人： Songping Yu , Mohamed Othman , Ryan B McNamara , Sean King
IPC分类号： F16H61/68 , F16H59/44 , F16H61/00 , F16H61/02
CPC分类号： F16H61/68 , B60R16/0236 , F16H59/44 , F16H61/0213 , F16H63/42 , F16H2061/0015 , F16H2061/0216 , F16H2061/022 , F16H2063/426 , Y02T10/84
摘要： Transmission gear shift control techniques can include calculating, at a controller of a vehicle powered by an internal combustion engine, the controller including one or more processors, brake specific fuel consumption (BSFC) for each of: (i) a current gear of a transmission of the vehicle, (ii) a lower gear than the current gear of the transmission, and (iii) a higher gear than the current gear of the transmission, wherein the transmission is one of a manual transmission and an automatic transmission operating in a manual mode. The techniques can include determining, at the controller, which of the current gear, the lower gear, and the higher gear has a smallest BSFC to obtain a desired gear of the transmission. The techniques can also include outputting, from the controller, an indication to shift the transmission to the desired gear.
摘要翻译：变速器变速控制技术可以包括在由内燃机驱动的车辆的控制器下计算控制器，该控制器包括一个或多个处理器，用于以下各项的制动特定燃料消耗（BSFC）：（i）变速器的当前齿轮，（ii）比传动装置的当前齿轮低的档位，以及（iii）比变速器的当前档位高的档位，其中变速器是手动变速器和在手动操作中的自动变速器之一模式。这些技术可以包括在控制器处确定当前齿轮，下齿轮和较高齿轮中的哪一个具有最小BSFC以获得变速器的期望齿轮。这些技术还可以包括从控制器输出将变速器换档到期望档位的指示。

4. 发明申请

US20090321795A1 SELECTIVE FORMATION OF DIELECTRIC ETCH STOP LAYERS 失效
标题翻译：选择性形成电介质蚀刻层
公开(公告)号：US20090321795A1
公开(公告)日：2009-12-31
申请号：US12165515
申请日：2008-06-30
申请人： Sean King , Jason Klaus
发明人： Sean King , Jason Klaus
IPC分类号： H01L21/28 , H01L29/423
CPC分类号： H01L21/28052 , H01L21/76834 , H01L21/76889 , H01L29/4933 , H01L29/7833
摘要： Methods to selectively form a dielectric etch stop layer over a patterned metal feature. Embodiments include a transistor incorporating such an etch stop layer over a gate electrode. In accordance with certain embodiments of the present invention, a metal is selectively formed on the surface of the gate electrode which is then converted to a silicide or germanicide. In other embodiments, the metal selectively formed on the gate electrode surface enables a catalytic growth of a silicon or germanium mesa over the gate electrode. At least a portion of the silicide, germanicide, silicon mesa or germanium mesa is then oxidized, nitridized, or carbonized to form a dielectric etch stop layer over the gate electrode only.
摘要翻译：选择性地在图案化的金属特征上形成介电蚀刻停止层的方法。实施例包括在栅电极上并入有这种蚀刻停止层的晶体管。根据本发明的某些实施方案，在栅电极的表面上选择性地形成金属，然后将其转化为硅化物或锗酸盐。在其他实施例中，选择性地形成在栅电极表面上的金属使得能够在栅电极上催化生长硅或锗台面。硅化物，锗化硅，硅台面或锗台面的至少一部分然后被氧化，氮化或碳化，以在栅电极上形成电介质蚀刻停止层。

5. 发明申请

US20130292835A1 CONFORMAL LOW TEMPERATURE HERMETIC DIELECTRIC DIFFUSION BARRIERS 有权
标题翻译：一致的低温电磁扩散障碍
公开(公告)号：US20130292835A1
公开(公告)日：2013-11-07
申请号：US13976835
申请日：2011-12-20
申请人： Sean King , Hui Jae Yoo , Sreenivas Kosaraju , Timothy Glassman
发明人： Sean King , Hui Jae Yoo , Sreenivas Kosaraju , Timothy Glassman
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76831 , H01L21/02178 , H01L21/022 , H01L21/0228 , H01L21/76802 , H01L21/7682 , H01L21/76829 , H01L21/76877 , H01L23/522 , H01L23/5222 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.
摘要翻译：适合于3D地形的电介质扩散屏障的保形密封电介质膜。在实施例中，电介质扩散阻挡层包括介电层，例如金属氧化物，其可以通过原子层沉积（ALD）技术沉积，其共形度和密度大于常规的基于二氧化硅的膜沉积的二氧化硅基膜用于较薄连续密封扩散屏障的PECVD工艺。在另外的实施例中，扩散阻挡层是包括高k电介质层和低k或中间介电层（例如双层）的多层膜，以降低扩散阻挡层的介电常数。在其它实施方案中，形成高k电介质层（例如金属硅酸盐）的硅酸盐，以通过调节硅酸盐的硅含量来降低扩散阻挡层的k值，同时保持高的膜保形性和密度。

6. 发明授权

US08120114B2 Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate 有权
标题翻译：晶体管具有蚀刻停止层，该蚀刻停止层包括选择性地形成在金属栅极上的金属化合物
公开(公告)号：US08120114B2
公开(公告)日：2012-02-21
申请号：US11646764
申请日：2006-12-27
申请人： Andrew Ott , Sean King , Ajay Sharma
发明人： Andrew Ott , Sean King , Ajay Sharma
IPC分类号： H01L29/40 , H01L29/78 , H01L23/48
CPC分类号： H01L21/76834 , H01L21/2807 , H01L21/28079 , H01L21/76826 , H01L21/7685 , H01L21/76856 , H01L21/76886 , H01L21/76888
摘要： In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.
摘要翻译：一方面，装置可以包括晶体管的金属栅极。蚀刻停止层可以选择性地形成在金属栅上。蚀刻停止层可以包括金属化合物。绝缘层可以在蚀刻停止层之上。导电结构可以通过绝缘层包括到金属栅极。还公开了制造这种晶体管的方法。

7. 发明授权

US08399317B2 Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate, and method therefor 有权
标题翻译：具有包括选择性地形成在金属栅极上的金属化合物的蚀刻停止层的晶体管及其方法
公开(公告)号：US08399317B2
公开(公告)日：2013-03-19
申请号：US13273771
申请日：2011-10-14
申请人： Andrew Ott , Sean King , Ajay Sharma
发明人： Andrew Ott , Sean King , Ajay Sharma
IPC分类号： H01L21/336 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/2807 , H01L21/28079 , H01L21/76826 , H01L21/7685 , H01L21/76856 , H01L21/76886 , H01L21/76888
摘要： In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.
摘要翻译：一方面，装置可以包括晶体管的金属栅极。蚀刻停止层可以选择性地形成在金属栅上。蚀刻停止层可以包括金属化合物。绝缘层可以在蚀刻停止层之上。导电结构可以通过绝缘层包括到金属栅极。还公开了制造这种晶体管的方法。

8. 发明授权

US08178436B2 Adhesion and electromigration performance at an interface between a dielectric and metal 有权
标题翻译：电介质和金属之间界面处的粘附和电迁移性能
公开(公告)号：US08178436B2
公开(公告)日：2012-05-15
申请号：US11644743
申请日：2006-12-21
申请人： Sean King , Jason Klaus
发明人： Sean King , Jason Klaus
IPC分类号： H01L21/4763 , H01L21/70 , H01L21/44 , H01L21/469 , H01L23/48
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having improved adhesion and electromigration performance and methods to fabricate thereof are described. A tensile capping layer is formed on a first conductive layer on a substrate. A compressive capping layer is formed on the tensile capping layer. Next, an interlayer dielectric layer is formed on the compressive capping layer. Further, a first opening is formed in the ILD layer using a first chemistry. A second opening is formed in the tensile capping layer and the compressive capping layer using a second chemistry. Next, a second conductive layer is formed in the first opening and the second opening.
摘要翻译：描述了具有改善的粘附性和电迁移性能的互连结构及其制造方法。在基板上的第一导电层上形成拉伸覆盖层。在拉伸覆盖层上形成压缩封盖层。接下来，在压缩覆盖层上形成层间电介质层。此外，使用第一化学物质在ILD层中形成第一开口。使用第二化学物质在拉伸覆盖层和压缩覆盖层中形成第二开口。接下来，在第一开口和第二开口中形成第二导电层。

9. 发明申请

US20120074387A1 MICROELECTRONIC TRANSISTOR HAVING AN EPITAXIAL GRAPHENE CHANNEL LAYER 失效
标题翻译：具有外延图形通道层的微电子晶体管
公开(公告)号：US20120074387A1
公开(公告)日：2012-03-29
申请号：US12888979
申请日：2010-09-23
申请人： Sean King
发明人： Sean King
IPC分类号： H01L29/66 , H01L21/36
CPC分类号： H01L29/1606 , H01L21/02057 , H01L21/02381 , H01L21/02447 , H01L21/02527 , H01L21/02581 , H01L21/0262 , H01L29/66742 , H01L29/7781 , H01L29/78603 , H01L29/78684
摘要： The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to forming a graphene layer as a channel layer for a microelectronic transistor.
摘要翻译：本公开涉及微电子晶体管制造领域，更具体地说，涉及形成石墨烯层作为微电子晶体管的沟道层。

10. 发明授权

US07816218B2 Selective deposition of amorphous silicon films on metal gates 有权
标题翻译：在金属栅极上选择性沉积非晶硅膜
公开(公告)号：US07816218B2
公开(公告)日：2010-10-19
申请号：US12228615
申请日：2008-08-14
申请人： Jason Klaus , Sean King , Willy Rachmady
发明人： Jason Klaus , Sean King , Willy Rachmady
IPC分类号： H01L21/00
CPC分类号： H01L21/76834 , H01L21/31105 , H01L21/76816 , H01L29/6659 , H01L29/7833
摘要： A microelectronic device includes a metal gate with a metal gate upper surface. The metal gate is disposed in an interlayer dielectric first layer. The interlayer dielectric first layer also has an upper surface that is coplanar with the metal gate upper surface. A dielectric etch stop layer is disposed on the metal gate upper surface but not on the interlayer dielectric first layer upper surface.
摘要翻译：微电子器件包括具有金属栅极上表面的金属栅极。金属栅极设置在层间电介质第一层中。层间电介质第一层还具有与金属栅极上表面共面的上表面。电介质蚀刻停止层设置在金属栅极上表面上，但不设置在层间电介质第一层上表面上。

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