会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明授权
    • Clock recovery digital phase-locked loop
    • 时钟恢复数字锁相环
    • US4680780A
    • 1987-07-14
    • US858425
    • 1986-05-01
    • Agoston AgostonRobert G. Sparkes
    • Agoston AgostonRobert G. Sparkes
    • H03L7/06H04L7/033H03D3/24H03D3/18
    • H04L7/0331
    • A digital phase-locked loop circuit for recovering an external clock signal from an input serial data stream includes an up/down counter responsive to both the serial data stream and to the clock pulse output of a variable divider driven by an external clock. The up/down counter counts in a direction which depends upon whether the input data stream leads or lags the variable divider's clock pulse output. The output of the up/down counter drives an n-bit memory and a comparator such that the n-bit memory stores the n most significant bits of the up/down counter for a predetermined period of time and then provides them to the comparator for comparison with the present value of the up/down counter. A binary code is provided to the variable divider to determine its divisor depending upon whether the memory count is greater than, equal to, or less than the present count of the up/down counter. This enables an external clock to be synchronized to the input data stream while removing random noise.
    • 用于从输入串行数据流恢复外部时钟信号的数字锁相环电路包括响应于串行数据流和由外部时钟驱动的可变分频器的时钟脉冲输出的上/下计数器。 上/下计数器在取决于输入数据流是否导通或滞后可变分频器的时钟脉冲输出的方向上进行计数。 上/下计数器的输出驱动n位存储器和比较器,使得n位存储器在预定时间段内存储加/减计数器的n个最高有效位,然后将它们提供给比较器 与上下计数器的现值进行比较。 根据存储器计数是否大于,等于或小于上/下计数器的当前计数,将二进制代码提供给可变分频器以确定其除数。 这使外部时钟能够同步到输入数据流,同时消除随机噪声。
    • 5. 发明授权
    • Equivalent time pseudorandom sampling system
    • 等效时间伪随机抽样系统
    • US4678345A
    • 1987-07-07
    • US858424
    • 1986-05-01
    • Agoston Agoston
    • Agoston Agoston
    • G01R13/32G01R13/34G01R19/255G04F5/00G04F8/00
    • G01R19/255G01R13/32G01R13/34G04F5/00
    • An equivalent time pseudorandom sampling system samples a repetitive waveform within each of several narrow acquisition windows bounding repetitive sections of the waveform in order to obtain equivalent time sample data characterizing the shape of the waveform included within the acquisition windows. The period between successive triggering events is measured and sampling is delayed following an initiating triggering event by delay time adjusted according to the measured period so as to maximize the probability that sampling will occur within an acquisition window. The time difference between samples and subsequent triggering event is measured with high accuracy and resolution utilizing a time interval measurement system based on a dual vernier interpolation.
    • 等效时间伪随机采样系统在围绕波形的重复部分的几个窄采集窗口的每一个采样重复波形,以获得表征包含在采集窗口内的波形的形状的等效时间采样数据。 测量连续触发事件之间的周期,并且根据测量周期调整延迟时间后的起始触发事件之后采样被延迟,以便最大化在采集窗口内进行采样的概率。 使用基于双游标内插的时间间隔测量系统,以高精度和分辨率测量采样和后续触发事件之间的时间差。
    • 9. 发明授权
    • Travelling wave sampler
    • 行波采样器
    • US4647795A
    • 1987-03-03
    • US845900
    • 1986-03-28
    • Agoston Agoston
    • Agoston Agoston
    • G01R13/34G01R13/20G01R15/00G11C27/02H03K17/16H03K17/74
    • G11C27/026
    • A travelling wave sampler has an input terminal for receiving an input signal to be sampled. A first diode has its anode connected to the input terminal, whereas a second diode has its cathode connected to the input terminal. A first delay line is connected between the cathode of the first diode and the anode of a third diode, and a second delay line is connected between the anode of the second diode and the cathode of a fourth diode. A strobe generator provides negative-going strobe pulses to the cathode of the third diode through a first strobe capacitor and provides positive-going strobe pulses to the anode of the fourth diode through a second strobe capacitor. The third and fourth diodes are maintained in zero biased condition when strobe pulses are not provided by the strobe generator and are forward biased during the strobe pulses. At the end of a strobe pulse, the charge that was accumulated on the strobe capacitors during the strobe pulse drives the third and fourth diodes into reverse biased condition.
    • 行波采样器具有用于接收要采样的输入信号的输入端。 第一二极管的阳极连接到输入端,而第二二极管的阴极连接到输入端。 第一延迟线连接在第一二极管的阴极和第三二极管的阳极之间,第二延迟线连接在第二二极管的阳极和第四二极管的阴极之间。 选通发生器通过第一选通电容器向第三二极管的阴极提供负向选通脉冲,并通过第二选通电容器向第四二极管的阳极提供正向选通脉冲。 当选通脉冲不由选通脉冲发生器提供并且在选通脉冲期间被正向偏置时,第三和第四二极管保持在零偏置状态。 在选通脉冲结束时,在选通脉冲期间累积在选通电容器上的电荷将第三和第四二极管驱动成反向偏置状态。