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1. 发明授权

US5566178A Method and system for improving the performance of a token ring network 失效
标题翻译：提高令牌环网络性能的方法和系统
公开(公告)号：US5566178A
公开(公告)日：1996-10-15
申请号：US363425
申请日：1994-12-22
申请人： Adrian S. Butter , Chang Y. Kao , James P. Kuruts
发明人： Adrian S. Butter , Chang Y. Kao , James P. Kuruts
IPC分类号： H04L12/433
CPC分类号： H04L12/433
摘要： A system and method for implementing a new protocol that uses new data structures in order to improve the performance of a token ring without changing its topology or degrading its fairness. A primary sender sends a data frame containing a data field addressed to a primary receiver. The protocol allows the primary receiver to enter "transmit mode" and assume another role as a secondary sender when the data frame is received and copied. The secondary sender overwrites the data field. Then, the secondary sender designates a secondary receiver to receive the update data and sends an acknowledgement message back to the primary sender to indicate that it has received data. The secondary receiver sends an acknowledgement to the secondary sender when the secondary transmission data is received. The primary sender checks for an acknowledgement from the primary receiver when the data frame returns. Then the primary sender transmits the data frame downstream. The primary sender regenerates a token and either releases it or seizes it based on whether it has more data to send. The secondary sender verifies the acknowledgement from the secondary receiver and returns to "listen mode".
摘要翻译：一种用于实现使用新数据结构的新协议的系统和方法，以便在不改变其拓扑或降低其公平性的情况下提高令牌环的性能。主发送方发送包含寻址到主接收机的数据字段的数据帧。该协议允许主接收机进入“发送模式”，并在接收和复制数据帧时承担另一个作为次要发送方的角色。辅助发送方覆盖数据字段。然后，辅助发送方指定接收更新数据的辅助接收器，并将确认消息发送回主发送方以指示其已经接收到数据。当接收到辅助传输数据时，辅助接收机向次要发送者发送确认。当数据帧返回时，主发送方检查主接收方的确认。然后主发送方将数据帧发送到下游。主发送方重新生成一个令牌，并根据是否有更多的数据发送，释放它或占用它。辅助发送者验证来自辅助接收机的确认并返回到“监听模式”。

2. 发明授权

US5528594A Method and system for implementing sub-tokens on a token ring network 失效
标题翻译：在令牌环网上实施子令牌的方法和系统
公开(公告)号：US5528594A
公开(公告)日：1996-06-18
申请号：US363432
申请日：1994-12-22
申请人： Adrian S. Butter , Chang Y. Kao , James P. Kuruts
发明人： Adrian S. Butter , Chang Y. Kao , James P. Kuruts
IPC分类号： H04L12/433 , H04L12/427
CPC分类号： H04L12/433
摘要： A method and system for increasing performance on a standard dual ring token ring by generating one or more sub-tokens so that multiple data transmissions can occur concurrently. Upon receipt of a data frame from the token holder, interface logic enables a receiver to generate a sub-token frame. The sub-token is used to notify the next downstream station that it may transmit data frames to other downstream stations. In this way, a second data transmission path can be established between downstream stations. In a similar manner, the receiver of a data frame sent by a sub-token owner will generate a sub-token frame for use by the next downstream station when its data arrives. Each sub-token is used to create a new sub-ring, thus allowing for concurrent data transmissions. Each new sub-ring must obey token ring protocol to avoid data collisions.
摘要翻译：一种用于通过生成一个或多个子令牌来提高标准双环令牌环的性能以便多个数据传输可以同时发生的方法和系统。接口逻辑在从令牌持有者接收到数据帧时，使得接收器能够生成子令牌帧。子令牌用于通知下一个下游站它可以向其他下游站传输数据帧。以这种方式，可以在下游站之间建立第二数据传输路径。以类似的方式，由子令牌所有者发送的数据帧的接收者将产生一个子令牌帧，以供下一个下游站在其数据到达时使用。每个子令牌用于创建新的子环，从而允许并发数据传输。每个新的子环必须遵守令牌环协议以避免数据冲突。

3. 发明授权

US5432848A DES encryption and decryption unit with error checking 失效
标题翻译： DES加密和解密单元进行错误检查
公开(公告)号：US5432848A
公开(公告)日：1995-07-11
申请号：US228474
申请日：1994-04-15
申请人： Adrian S. Butter , Chang Y. Kao , James P. Kuruts
发明人： Adrian S. Butter , Chang Y. Kao , James P. Kuruts
IPC分类号： H04L9/06 , H04K1/00
CPC分类号： H04L9/0625 , H04L2209/12 , H04L2209/34
摘要： An improved DES unit internally checks whether the DES algorithm is being performed without error. A standard DES algorithm performs an initial permutation of input data and then multiple rounds or iterations of the following: expanding part of a result of the initial permutation for the first iteration and a result of the previous iteration for the subsequent iterations, exclusive ORing a result of the expansion with key bits, performing a selection function on a result of the exclusive ORing, permuting a result of the selection function, and exclusive ORing a result of the permuting. In the improved DES unit, data check bits that correspond to the input data which has been expanded are exclusive NORed with key check bits that correspond to the key, and a result of the exclusive NORing is checked against a result of the exclusive ORing to identify any errors in the operation of the basic DES unit. Also, a check selection function is performed on the result of the exclusive ORing. A result of the check selection function is exclusive NORed with data check bits for another part of the input data to yield input data for input to the expanding function for a next iteration. Also, the improved DES unit checks for accuracy in processing an input key by permuted choicing the input key, key shifting a result of the permuted choicing, and checking a result of the key shifting against key check bits which correspond to the input key and bypass the permuted choicing and key shifting functions.
摘要翻译：改进的DES单元内部检查是否正在执行DES算法而没有错误。标准DES算法执行输入数据的初始置换，然后执行以下的多次或多次迭代：扩展第一次迭代的初始置换结果的一部分和后续迭代的先前迭代的结果，将结果异或使用关键位进行扩展，对异或运算的结果执行选择功能，对选择功能的结果进行置换，并对排列结果进行异或运算。在改进的DES单元中，对应于已经扩展的输入数据的数据校验位与对应于该键的密钥校验位是异或，并且针对异或运算的结果来检查异或的结果以识别基本的DES单元的运行中的任何错误。此外，对异或运算的结果执行检查选择功能。检查选择功能的结果是异或运算，数据校验位用于输入数据的另一部分，以产生用于下一次迭代的扩展功能输入的输入数据。此外，改进的DES单元通过对输入键进行置换来选择输入键的精度来检查输入键的精度，键移动置换的选择的结果，以及检查与对应于输入键和旁路的键检查位的键移位的结果重置的选择和键移动功能。

4. 发明授权

US5381480A System for translating encrypted data 失效
标题翻译：用于翻译加密数据的系统
公开(公告)号：US5381480A
公开(公告)日：1995-01-10
申请号：US124151
申请日：1993-09-20
申请人： Adrian S. Butter , Brian S. Finkel , Chang-Yung Kao , Sivarama K. Kodukula , James P. Kuruts
发明人： Adrian S. Butter , Brian S. Finkel , Chang-Yung Kao , Sivarama K. Kodukula , James P. Kuruts
IPC分类号： H04L9/06 , H04L9/16
CPC分类号： H04L9/0625 , H04L2209/125 , H04L2209/24
摘要： A system translates a first group of cipher blocks based on a first encryption key to a second group of respective cipher blocks based on a second encryption key. Respective cipher blocks of the first and second groups represent the same data. The system comprises decryption hardware for sequentially decrypting the cipher blocks of the first group based on the first key. Encryption hardware is coupled to receive decrypted blocks output from the decryption hardware and sequentially encrypts the decrypted blocks into respective cipher blocks of the second group based on the second encryption key. A control unit controls the encryption hardware to encrypt the decrypted blocks into the respective cipher blocks of the second group while the decryption hardware decrypts cipher blocks of the first group. Consequently, decryption and encryption operations occur in parallel and the translation process is expedited.
摘要翻译：系统基于第二加密密钥将基于第一加密密钥的第一组密码块转换为第二组相应加密块。第一组和第二组的各个密码块表示相同的数据。该系统包括用于基于第一密钥顺序地解密第一组的密码块的解密硬件。加密硬件被耦合以接收从解密硬件输出的解密块，并且基于第二加密密钥将解密的块顺序地加密成第二组的相应加密块。控制单元控制加密硬件将解密块加密成第二组的相应加密块，同时解密硬件解密第一组的加密块。因此，解密和加密操作并行发生，并且加速了翻译过程。

5. 发明授权

US5317638A Performance enhancement for ANSI X3.92 data encryption algorithm standard 失效
标题翻译： ANSI X3.92数据加密算法标准的性能提升
公开(公告)号：US5317638A
公开(公告)日：1994-05-31
申请号：US916777
申请日：1992-07-17
申请人： Chang Y. Kao , James P. Kuruts , Sivarama K. Kodukula
发明人： Chang Y. Kao , James P. Kuruts , Sivarama K. Kodukula
IPC分类号： G06F12/00 , G09C1/00 , G09C1/10 , H04L9/06 , H04K1/00
CPC分类号： H04L9/0625
摘要： ANSI X3.92 Data Encryption algorithm is public knowledge, and is widely used where data security and integrity is vital, such as commercial banks, secret service organizations etc. Even though this algorithm is feasible to implement in software, it is impractical to achieve desired performance for most of the applications. Hence, a hardware solution is highly recommended. Prior art DES hardware in CMOS technology served performance needs of low-end and mid-range systems only, due to the technology constraints. However, some of these constraints are removed through the technology breakthroughs and the current CMOS is well suited for high performance applications. While prior art DES designs allowed one round per cycle to minimize the cell count, the current technology allows of multiple rounds per cycle due to the denser CMOS chip technology. In order to maximize the number of rounds for a given cycle time, careful study of algorithm to determine the critical paths from a logic implementation perspective is required. This invention identifies one such path in f-function of the DES algorithm, where the expanded data and the key is XOR'd prior to entering S-function. It is mathematically proven that if the left half of the input data is expanded and XOR'ed with the second key at the same time the right half of the input data which is still going through its XOR, S-function, permute and expansion, then this expanded result can be immediately XOR'ed with the left input data being expanded and XOR'ed in parallel. The resulting output can be used as input to the next S-function, thus eliminating a stage of expansion and XOR logic for all subsequent S-function inputs in rounds 2 through 15.
摘要翻译： ANSI X3.92数据加密算法是公共知识，在数据安全和完整性至关重要的情况下被广泛使用，如商业银行，秘密服务机构等。即使这种算法在软件中实现是可行的，实现期望是不切实际的大多数应用的性能。因此，强烈建议使用硬件解决方案。由于技术上的限制，现有技术的CMOS技术的DES硬件只能满足低端和中端系统的性能需求。然而，通过技术突破，可以消除其中的一些限制，目前的CMOS非常适合高性能应用。虽然现有技术的DES设计允许每个周期一个循环以使细胞计数最小化，但由于采用更密集的CMOS芯片技术，目前的技术允许每个周期多轮。为了最大化给定循环时间的轮数，需要从逻辑实现的角度仔细研究确定关键路径的算法。本发明在DES算法的f函数中识别一个这样的路径，其中扩展的数据和密钥在进入S函数之前是异或的。在数学上证明，如果输入数据的左半部分在第二个键的同时被扩展并且与正在经历其XOR，S函数，置换和扩展的输入数据的右半部分相异，那么这个扩展结果可以立即异或左输入数据被扩展并并行XOR。所得到的输出可以用作下一个S函数的输入，从而消除了第2到15周期中所有后续S函数输入的扩展阶段和异或逻辑。

6. 发明授权

US07953510B2 System and method for semiconductor identification chip read out 失效
标题翻译：用于半导体识别芯片的系统和方法读出
公开(公告)号：US07953510B2
公开(公告)日：2011-05-31
申请号：US11855000
申请日：2007-09-13
申请人： Robert Walter Berry, Jr. , Christopher R. Conley , Christopher J. Kuruts , James P. Kuruts
发明人： Robert Walter Berry, Jr. , Christopher R. Conley , Christopher J. Kuruts , James P. Kuruts
IPC分类号： G06F19/00
CPC分类号： H01L23/544 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： A system and method for semiconductor identification chip read out is presented. A user uses a stand-alone handheld device to extract product data, which includes manufacturing process attributes, from a semiconductor device. The semiconductor device couples to the hand held device through a subset of pins, such as a power pin, a ground pin, a clock in pin, and a data out pin. When coupled, the handheld device provides a clock signal to the semiconductor device. In turn, on chip logic within the semiconductor device detects the clock signal and gathers internal product data. Once gathered, the on chip logic provides the product data to the hand held device through the data out pin for a user to view. As a result, the user may track semiconductor devices more efficiently.
摘要翻译：提出了一种用于半导体识别芯片读出的系统和方法。用户使用独立的手持设备从半导体器件提取包括制造工艺属性的产品数据。半导体器件通过诸如电源引脚，接地引脚，引脚时钟和数据输出引脚的引脚子集耦合到手持设备。当耦合时，手持设备向半导体器件提供时钟信号。反过来，半导体器件内的片上逻辑检测时钟信号并收集内部产品数据。一旦收集，片上逻辑通过数据输出引脚向手持设备提供产品数据，供用户查看。结果，用户可以更有效地跟踪半导体器件。

7. 发明申请

US20080059103A1 System and Method for Implementing a Programmable DMA Master With Date Checking Utilizing a Drone System Controller 失效
标题翻译：使用无人机系统控制器实现可编程DMA主机的日期检查的系统和方法
公开(公告)号：US20080059103A1
公开(公告)日：2008-03-06
申请号：US11470282
申请日：2006-09-06
申请人： Robert W. Berry , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
IPC分类号： G06F19/00 , G11C29/00
CPC分类号： G11C29/48 , G06F11/26
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with date checking utilizing a drone system controller. According to a preferred embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译：一种方法，系统和计算机可用介质，用于使用无人机系统控制器实现具有日期检查的可编程DMA主机。根据本发明的优选实施例，无人机处理器生成随机数据的集合，并将随机数据集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。无人机处理器将随机数据集合的第三副本写入处理器存储器。当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。

8. 发明申请

US20090076641A1 System and Method for Semiconductor Identification Chip Read Out 失效
标题翻译：半导体识别芯片读出系统和方法
公开(公告)号：US20090076641A1
公开(公告)日：2009-03-19
申请号：US11855000
申请日：2007-09-13
申请人： Robert Walter Berry, JR. , Christopher R. Conley , Christopher J. Kuruts , James P. Kuruts
发明人： Robert Walter Berry, JR. , Christopher R. Conley , Christopher J. Kuruts , James P. Kuruts
IPC分类号： G06F19/00
CPC分类号： H01L23/544 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： A system and method for semiconductor identification chip read out is presented. A user uses a stand-alone handheld device to extract product data, which includes manufacturing process attributes, from a semiconductor device. The semiconductor device couples to the hand held device through a subset of pins, such as a power pin, a ground pin, a clock in pin, and a data out pin. When coupled, the handheld device provides a clock signal to the semiconductor device. In turn, on chip logic within the semiconductor device detects the clock signal and gathers internal product data. Once gathered, the on chip logic provides the product data to the hand held device through the data out pin for a user to view. As a result, the user may track semiconductor devices more efficiently.
摘要翻译：提出了一种用于半导体识别芯片读出的系统和方法。用户使用独立的手持设备从半导体器件提取包括制造工艺属性的产品数据。半导体器件通过诸如电源引脚，接地引脚，引脚时钟和数据输出引脚的引脚子集耦合到手持设备。当耦合时，手持设备向半导体器件提供时钟信号。反过来，半导体器件内的片上逻辑检测时钟信号并收集内部产品数据。一旦收集，片上逻辑通过数据输出引脚将产品数据提供给手持设备，供用户查看。结果，用户可以更有效地跟踪半导体器件。

9. 发明申请

US20080312863A1 SYSTEM AND METHOD FOR IMPLEMENTING A PROGRAMMABLE DMA MASTER WITH DATE CHECKING UTILIZING A DRONE SYSTEM CONTROLLER 失效
标题翻译：用于执行可编程DMA主机的系统和方法，日期检查使用DRONE系统控制器
公开(公告)号：US20080312863A1
公开(公告)日：2008-12-18
申请号：US12187199
申请日：2008-08-06
申请人： Robert W. Berry, JR. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry, JR. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
IPC分类号： G11C29/00 , G06F19/00
CPC分类号： G11C29/48 , G06F11/26
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译：一种用于使用无人机系统控制器实现具有数据检查的可编程DMA主机的方法，系统和计算机可用介质。根据本发明的实施例，无人机处理器生成随机数据的集合，并将随机数据的集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。无人机处理器将随机数据集合的第三副本写入处理器存储器。当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。

10. 发明授权

US08165847B2 Implementing a programmable DMA master with write inconsistency determination 失效
标题翻译：实现具有写入不一致性确定的可编程DMA主机
公开(公告)号：US08165847B2
公开(公告)日：2012-04-24
申请号：US12187199
申请日：2008-08-06
申请人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry, Jr. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
IPC分类号： G06F11/30 , G11C29/00
CPC分类号： G11C29/48 , G06F11/26
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译：一种用于使用无人机系统控制器实现具有数据检查的可编程DMA主机的方法，系统和计算机可用介质。根据本发明的实施例，无人机处理器生成随机数据的集合，并将随机数据的集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。无人机处理器将随机数据集合的第三副本写入处理器存储器。当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。

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