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1. 发明授权

US09141546B2 System and method for managing transactions 有权
标题翻译：用于管理事务的系统和方法
公开(公告)号：US09141546B2
公开(公告)日：2015-09-22
申请号：US13682781
申请日：2012-11-21
申请人： Adi Habusha , Gil Stoler , Said Bshara , Nafea Bshara
发明人： Adi Habusha , Gil Stoler , Said Bshara , Nafea Bshara
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0831 , G06F12/0833 , G06F12/0855 , G06F2212/62 , G06F2212/621 , G11C7/1072
摘要： A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.
摘要翻译：一种用于写入数据的方法，所述方法可以包括：由接口模块接收或生成用于对数据单元执行第一地址的相干写操作的数据单元相干写入请求; 通过接口模块和包括高速缓存和高速缓存控制器的电路接收指示存储在第一地址的内容的最新版本被存储在高速缓存中的高速缓存一致性指示符; 并且由所述接口模块指示所述高速缓存控制器使存储所述第一地址的最新版本的所述高速缓存的高速缓存行无效，而不将所述第一地址处存储的所述内容的最新版本从所述高速缓存发送到存储器模块如果数据单元的长度等于高速缓存线的长度，则与缓存不同。

2. 发明申请

US20140143487A1 SYSTEM AND METHOD FOR MANAGING TRANSACTIONS 有权
标题翻译：用于管理交易的系统和方法
公开(公告)号：US20140143487A1
公开(公告)日：2014-05-22
申请号：US13682781
申请日：2012-11-21
申请人： Adi Habusha , Gil Stoler , Said Bshara , Nafea Bshara
发明人： Adi Habusha , Gil Stoler , Said Bshara , Nafea Bshara
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0831 , G06F12/0833 , G06F12/0855 , G06F2212/62 , G06F2212/621 , G11C7/1072
摘要： A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.
摘要翻译：一种用于写入数据的方法，所述方法可以包括：由接口模块接收或生成用于对数据单元执行第一地址的相干写操作的数据单元相干写入请求; 通过接口模块和包括高速缓存和高速缓存控制器的电路接收指示存储在第一地址的内容的最新版本被存储在高速缓存中的高速缓存一致性指示符; 并且由所述接口模块指示所述高速缓存控制器使存储所述第一地址的最新版本的所述高速缓存的高速缓存行无效，而不将所述第一地址处存储的所述内容的最新版本从所述高速缓存发送到存储器模块如果数据单元的长度等于高速缓存线的长度，则与缓存不同。

3. 发明授权

US08892784B2 Adaptive apparatus 有权
标题翻译：自适应装置
公开(公告)号：US08892784B2
公开(公告)日：2014-11-18
申请号：US13674121
申请日：2012-11-12
申请人： Adi Habusha , Rabeeh Khoury , Nafea Bshara
发明人： Adi Habusha , Rabeeh Khoury , Nafea Bshara
IPC分类号： G06F3/00 , G06F15/173 , G06F13/00 , G06F9/44
CPC分类号： G06F9/4411
摘要： There may be provided an apparatus, that may include an input/output (IO) circuit; a micro-controller; a memory module that is arranged to store multiple type identification information and multiple type configuration information; wherein the multiple type identification information allows the apparatus to be identified as being of each one of multiple types of peripheral cards; and wherein the multiple type configuration information allows the apparatus to operate each one of the multiple types; wherein the micro-controller is arranged, following a selection of a selected type out of the multiple types: to expose, to a host—that is coupled to the apparatus, a selected portion of the multiple peripheral identification information that indicates that the apparatus has a functionality of a peripheral card of the selected type; and to configure the peripheral card to interact with the host as being a peripheral card of the selected type.
摘要翻译：可以提供一种可以包括输入/输出（IO）电路的装置; 微控制器存储模块，被配置为存储多种类型的识别信息和多种类型的配置信息; 其中所述多类型识别信息允许所述装置被识别为多种类型的外围卡中的每一种; 并且其中所述多类型配置信息允许所述设备操作所述多种类型中的每一种; 其中所述微控制器被布置为在多种类型中选择所选择的类型之后：将与所述设备耦合的主机公开为指示所述设备具有的所述多个外围设备识别信息的选定部分所选类型的外围卡的功能; 并配置外围卡与主机交互作为所选类型的外围卡。

4. 发明申请

US20140136734A1 ADAPTIVE APPARATUS 有权
标题翻译：自适应装置
公开(公告)号：US20140136734A1
公开(公告)日：2014-05-15
申请号：US13674121
申请日：2012-11-12
申请人： Adi Habusha , Rabeeh Khoury , Nafea Bshara
发明人： Adi Habusha , Rabeeh Khoury , Nafea Bshara
IPC分类号： G06F9/44
CPC分类号： G06F9/4411
摘要： There may be provided an apparatus, that may include an input/output (IO) circuit; a micro-controller; a memory module that is arranged to store multiple type identification information and multiple type configuration information; wherein the multiple type identification information allows the apparatus to be identified as being of each one of multiple types of peripheral cards; and wherein the multiple type configuration information allows the apparatus to operate each one of the multiple types; wherein the micro-controller is arranged, following a selection of a selected type out of the multiple types: to expose, to a host—that is coupled to the apparatus, a selected portion of the multiple peripheral identification information that indicates that the apparatus has a functionality of a peripheral card of the selected type; and to configure the peripheral card to interact with the host as being a peripheral card of the selected type.
摘要翻译：可以提供一种可以包括输入/输出（IO）电路的装置; 微控制器存储模块，被配置为存储多种类型的识别信息和多种类型的配置信息; 其中所述多类型识别信息允许所述装置被识别为多种类型的外围卡中的每一种; 并且其中所述多类型配置信息允许所述设备操作所述多种类型中的每一种; 其中所述微控制器被布置为在多种类型中选择所选择的类型之后：将与所述设备耦合的主机公开为指示所述设备具有的所述多个外围设备识别信息的选定部分所选类型的外围卡的功能; 并配置外围卡与主机交互作为所选类型的外围卡。

5. 发明授权

US08484421B1 Cache pre-fetch architecture and method 有权
标题翻译：缓存预取架构和方法
公开(公告)号：US08484421B1
公开(公告)日：2013-07-09
申请号：US12624242
申请日：2009-11-23
申请人： Tarek Rohana , Adi Habusha , Gil Stoler
发明人： Tarek Rohana , Adi Habusha , Gil Stoler
IPC分类号： G06F13/00 , G06F9/30
CPC分类号： G06F12/0857 , G06F9/3802 , G06F9/3814 , G06F12/0862
摘要： Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core, and a cache including a cache instruction port, a cache data port, and a port utilization circuitry configured to selectively fetch instructions through the cache instruction port and selectively pre-fetch instructions through the cache data port. Other embodiments are also described and claimed.
摘要翻译：本公开的实施例提供了一种包括处理核心的芯片系统（SOC），以及包括高速缓存指令端口，高速缓存数据端口和端口利用电路的高速缓存，其被配置为选择性地通过高速缓存指令端口获取指令，并且选择性地通过缓存数据端口预取指令。还描述和要求保护其他实施例。

6. 发明授权

US08898540B1 Counter update through atomic operation 有权
标题翻译：通过原子操作计数器更新
公开(公告)号：US08898540B1
公开(公告)日：2014-11-25
申请号：US13074817
申请日：2011-03-29
申请人： Dan Ilan , Adi Habusha , Noam Mizrahi
发明人： Dan Ilan , Adi Habusha , Noam Mizrahi
IPC分类号： G11C29/00 , G06F11/20 , G06F11/10 , G06F9/38
CPC分类号： G06F11/2053 , G06F9/3004 , G06F9/382 , G06F9/3853 , G06F11/1048 , G06F11/106
摘要： Some of the embodiments of the present disclosure provide a system-on-chip (SOC) that includes a plurality of processing cores; and a counter update module configured to atomically update a counter that is stored in a storage location, based on a counter update command received from a processing core of the plurality of processing cores; generate an ECC for the updated value of the counter; and write the updated value of the counter and the ECC to the storage location. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了包括多个处理核心的片上系统（SOC）; 以及计数器更新模块，被配置为基于从所述多个处理核心的处理核心接收的计数器更新命令，原子地更新存储在存储位置中的计数器; 为计数器的更新值生成一个ECC; 并将计数器和ECC的更新值写入存储位置。还描述和要求保护其他实施例。

7. 发明授权

US08756362B1 Methods and systems for determining a cache address 有权
标题翻译：用于确定缓存地址的方法和系统
公开(公告)号：US08756362B1
公开(公告)日：2014-06-17
申请号：US13028660
申请日：2011-02-16
申请人： Eitan Joshua , Adi Habusha
发明人： Eitan Joshua , Adi Habusha
IPC分类号： G06F12/06 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0895 , G06F12/084
摘要： A method and system are provided for determining a next available address for writing data to a cache memory. In one implementation, a method includes receiving a request for a candidate address in the cache memory, the cache memory divided into a plurality of banks. The method further includes determining a candidate address in each of the cache memory banks using an address determination algorithm, selecting one of the candidate addresses from among the determined candidate addresses using an address selection function different from the address determination algorithm, and returning the selected candidate address in response to the request.
摘要翻译：提供了一种用于确定用于将数据写入高速缓冲存储器的下一可用地址的方法和系统。在一个实现中，一种方法包括：接收对高速缓冲存储器中候选地址的请求，高速缓冲存储器被分成多个存储体。该方法还包括使用地址确定算法确定每个高速缓存存储体中的候选地址，使用不同于地址确定算法的地址选择功能从所确定的候选地址中选择一个候选地址，并返回所选择的候选地址响应请求。

8. 发明授权

US09037810B2 Pre-fetching of data packets 有权
标题翻译：预取数据包
公开(公告)号：US09037810B2
公开(公告)日：2015-05-19
申请号：US13038258
申请日：2011-03-01
申请人： Adi Habusha , Alon Pais , Rabeeh Khoury
发明人： Adi Habusha , Alon Pais , Rabeeh Khoury
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/08 , G06F12/0859 , G06F12/12 , G06F12/121
摘要： Some of the embodiments of the present disclosure provide a method comprising receiving a data packet, and storing the received data packet in a memory; generating a descriptor for the data packet, the descriptor including information for fetching at least a portion of the data packet from the memory; and in advance of a processing core requesting the at least a portion of the data packet to execute a processing operation on the at least a portion of the data packet, fetching the at least a portion of the data packet to a cache based at least in part on information in the descriptor. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了一种方法，包括接收数据分组，并将所接收的数据分组存储在存储器中; 生成所述数据分组的描述符，所述描述符包括用于从所述存储器取出所述数据分组的至少一部分的信息; 并且在处理核心之前，请求所述数据分组的至少一部分对所述数据分组的所述至少一部分执行处理操作，至少基于所述数据分组的至少一部分将所述数据分组的所述至少一部分提取到高速缓存部分描述符中的信息。还描述和要求保护其他实施例。

9. 发明授权

US08924652B2 Simultaneous eviction and cleaning operations in a cache 有权
标题翻译：缓存中的同时驱逐和清洁操作
公开(公告)号：US08924652B2
公开(公告)日：2014-12-30
申请号：US13439366
申请日：2012-04-04
申请人： Adi Habusha , Eitan Joshua , Shaul Chapman
发明人： Adi Habusha , Eitan Joshua , Shaul Chapman
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0864
摘要： Embodiments provide a method comprising receiving, at a cache associated with a central processing unit that is disposed on an integrated circuit, a request to perform a cache operation on the cache; in response to receiving and processing the request, determining that first data cached in a first cache line of the cache is to be written to a memory that is coupled to the integrated circuit; identifying a second cache line in the cache, the second cache line being complimentary to the first cache line; transmitting a single memory instruction from the cache to the memory to write to the memory (i) the first data from the first cache line and (ii) second data from the second cache line; and invalidating the first data in the first cache line, without invalidating the second data in the second cache line.
摘要翻译：实施例提供了一种方法，包括在与设置在集成电路上的中央处理单元相关联的高速缓存处接收在高速缓存上执行高速缓存操作的请求; 响应于接收和处理该请求，确定缓存在高速缓存的第一高速缓存行中的第一数据将被写入耦合到该集成电路的存储器; 识别所述高速缓存中的第二高速缓存行，所述第二高速缓存行与所述第一高速缓存行互补; 将单个存储器指令从所述高速缓存发送到所述存储器以向所述存储器（i）写入来自所述第一高速缓存行的所述第一数据和（ii）来自所述第二高速缓存行的第二数据; 并且使第一高速缓存行中的第一数据无效，而不使第二高速缓存行中的第二数据无效。

10. 发明申请

US20120260041A1 SIMULTANEOUS EVICTION AND CLEANING OPERATIONS IN A CACHE 有权
标题翻译：高速缓存中的同时运行和清除操作
公开(公告)号：US20120260041A1
公开(公告)日：2012-10-11
申请号：US13439366
申请日：2012-04-04
申请人： Adi Habusha , Eitan Joshua , Shaul Chapman
发明人： Adi Habusha , Eitan Joshua , Shaul Chapman
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0864
摘要： Embodiments provide a method comprising receiving, at a cache associated with a central processing unit that is disposed on an integrated circuit, a request to perform a cache operation on the cache; in response to receiving and processing the request, determining that first data cached in a first cache line of the cache is to be written to a memory that is coupled to the integrated circuit; identifying a second cache line in the cache, the second cache line being complimentary to the first cache line; transmitting a single memory instruction from the cache to the memory to write to the memory (i) the first data from the first cache line and (ii) second data from the second cache line; and invalidating the first data in the first cache line, without invalidating the second data in the second cache line.
摘要翻译：实施例提供了一种方法，包括在与设置在集成电路上的中央处理单元相关联的高速缓存处接收在高速缓存上执行高速缓存操作的请求; 响应于接收和处理该请求，确定缓存在高速缓存的第一高速缓存行中的第一数据将被写入耦合到该集成电路的存储器; 识别所述高速缓存中的第二高速缓存行，所述第二高速缓存行与所述第一高速缓存行互补; 将单个存储器指令从所述高速缓存发送到所述存储器以向所述存储器（i）写入来自所述第一高速缓存行的所述第一数据和（ii）来自所述第二高速缓存行的第二数据; 并且使第一高速缓存行中的第一数据无效，而不使第二高速缓存行中的第二数据无效。

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