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1. 发明授权

US08924652B2 Simultaneous eviction and cleaning operations in a cache 有权
标题翻译：缓存中的同时驱逐和清洁操作
公开(公告)号：US08924652B2
公开(公告)日：2014-12-30
申请号：US13439366
申请日：2012-04-04
申请人： Adi Habusha , Eitan Joshua , Shaul Chapman
发明人： Adi Habusha , Eitan Joshua , Shaul Chapman
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0864
摘要： Embodiments provide a method comprising receiving, at a cache associated with a central processing unit that is disposed on an integrated circuit, a request to perform a cache operation on the cache; in response to receiving and processing the request, determining that first data cached in a first cache line of the cache is to be written to a memory that is coupled to the integrated circuit; identifying a second cache line in the cache, the second cache line being complimentary to the first cache line; transmitting a single memory instruction from the cache to the memory to write to the memory (i) the first data from the first cache line and (ii) second data from the second cache line; and invalidating the first data in the first cache line, without invalidating the second data in the second cache line.
摘要翻译：实施例提供了一种方法，包括在与设置在集成电路上的中央处理单元相关联的高速缓存处接收在高速缓存上执行高速缓存操作的请求; 响应于接收和处理该请求，确定缓存在高速缓存的第一高速缓存行中的第一数据将被写入耦合到该集成电路的存储器; 识别所述高速缓存中的第二高速缓存行，所述第二高速缓存行与所述第一高速缓存行互补; 将单个存储器指令从所述高速缓存发送到所述存储器以向所述存储器（i）写入来自所述第一高速缓存行的所述第一数据和（ii）来自所述第二高速缓存行的第二数据; 并且使第一高速缓存行中的第一数据无效，而不使第二高速缓存行中的第二数据无效。

2. 发明申请

US20120260041A1 SIMULTANEOUS EVICTION AND CLEANING OPERATIONS IN A CACHE 有权
标题翻译：高速缓存中的同时运行和清除操作
公开(公告)号：US20120260041A1
公开(公告)日：2012-10-11
申请号：US13439366
申请日：2012-04-04
申请人： Adi Habusha , Eitan Joshua , Shaul Chapman
发明人： Adi Habusha , Eitan Joshua , Shaul Chapman
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0864
摘要： Embodiments provide a method comprising receiving, at a cache associated with a central processing unit that is disposed on an integrated circuit, a request to perform a cache operation on the cache; in response to receiving and processing the request, determining that first data cached in a first cache line of the cache is to be written to a memory that is coupled to the integrated circuit; identifying a second cache line in the cache, the second cache line being complimentary to the first cache line; transmitting a single memory instruction from the cache to the memory to write to the memory (i) the first data from the first cache line and (ii) second data from the second cache line; and invalidating the first data in the first cache line, without invalidating the second data in the second cache line.
摘要翻译：实施例提供了一种方法，包括在与设置在集成电路上的中央处理单元相关联的高速缓存处接收在高速缓存上执行高速缓存操作的请求; 响应于接收和处理该请求，确定缓存在高速缓存的第一高速缓存行中的第一数据将被写入耦合到该集成电路的存储器; 识别所述高速缓存中的第二高速缓存行，所述第二高速缓存行与所述第一高速缓存行互补; 将单个存储器指令从所述高速缓存发送到所述存储器以向所述存储器（i）写入来自所述第一高速缓存行的所述第一数据和（ii）来自所述第二高速缓存行的第二数据; 并且使第一高速缓存行中的第一数据无效，而不使第二高速缓存行中的第二数据无效。

3. 发明授权

US08756362B1 Methods and systems for determining a cache address 有权
标题翻译：用于确定缓存地址的方法和系统
公开(公告)号：US08756362B1
公开(公告)日：2014-06-17
申请号：US13028660
申请日：2011-02-16
申请人： Eitan Joshua , Adi Habusha
发明人： Eitan Joshua , Adi Habusha
IPC分类号： G06F12/06 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0895 , G06F12/084
摘要： A method and system are provided for determining a next available address for writing data to a cache memory. In one implementation, a method includes receiving a request for a candidate address in the cache memory, the cache memory divided into a plurality of banks. The method further includes determining a candidate address in each of the cache memory banks using an address determination algorithm, selecting one of the candidate addresses from among the determined candidate addresses using an address selection function different from the address determination algorithm, and returning the selected candidate address in response to the request.
摘要翻译：提供了一种用于确定用于将数据写入高速缓冲存储器的下一可用地址的方法和系统。在一个实现中，一种方法包括：接收对高速缓冲存储器中候选地址的请求，高速缓冲存储器被分成多个存储体。该方法还包括使用地址确定算法确定每个高速缓存存储体中的候选地址，使用不同于地址确定算法的地址选择功能从所确定的候选地址中选择一个候选地址，并返回所选择的候选地址响应请求。

4. 发明授权

US08760324B1 Synchronous multi-clock protocol converter 有权
标题翻译：同步多时钟协议转换器
公开(公告)号：US08760324B1
公开(公告)日：2014-06-24
申请号：US13339210
申请日：2011-12-28
申请人： Gil Stoler , Eitan Joshua , Shaul Chapman
发明人： Gil Stoler , Eitan Joshua , Shaul Chapman
IPC分类号： H03M7/00
CPC分类号： H03M5/02
摘要： Some of the embodiments of the present disclosure provide a method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了一种从与快速时钟信号相关联的快速时钟域传送数据到与慢时钟信号相关联的慢时钟域的方法，该方法包括：在快速时钟域期间从快速时钟域接收第一快速数据第一快速时钟周期，其中所述第一快速时钟周期是第一慢时钟周期中的第一全快时钟周期; 并且在第一慢时钟周期的第一个全快速时钟周期期间将接收的第一快速数据传播到慢时钟域。还描述和要求保护其他实施例。

5. 发明授权

US08089378B1 Synchronous multi-clock protocol converter 有权
标题翻译：同步多时钟协议转换器
公开(公告)号：US08089378B1
公开(公告)日：2012-01-03
申请号：US12706605
申请日：2010-02-16
申请人： Gil Stoler , Eitan Joshua , Shaul Chapman
发明人： Gil Stoler , Eitan Joshua , Shaul Chapman
IPC分类号： H03M7/00
CPC分类号： H03M5/02
摘要： Some of the embodiments of the present disclosure provide a method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了一种从与快速时钟信号相关联的快速时钟域传送数据到与慢时钟信号相关联的慢时钟域的方法，该方法包括：在快速时钟域期间从快速时钟域接收第一快速数据第一快速时钟周期，其中所述第一快速时钟周期是第一慢时钟周期中的第一全快时钟周期; 并且在第一慢时钟周期的第一个全快速时钟周期期间将接收的第一快速数据传播到慢时钟域。还描述和要求保护其他实施例。

6. 发明授权

US06988237B1 Error-correction memory architecture for testing production errors 失效
标题翻译：用于测试生产错误的纠错内存架构
公开(公告)号：US06988237B1
公开(公告)日：2006-01-17
申请号：US10752174
申请日：2004-01-06
申请人： Yosef Solt , Eitan Joshua
发明人： Yosef Solt , Eitan Joshua
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G06F11/2215 , G11C29/42 , G11C2029/0405
摘要： An integrated circuit, having a method therefor, includes a memory including a plurality of memory lines, each memory line including a plurality of data cells each to store a data bit, and a plurality of error-correction (EC) cells each to store an EC bit corresponding to the data bits stored in the data cells of the memory line; an EC input circuit to generate the EC bits based on the corresponding data bits; an EC output circuit including an EC correction circuit to correct errors in the bits read from the data cells of each of the memory lines in accordance with the bits read from the EC cells of the memory line; and a switch including first inputs to receive the EC bits from the EC input circuit, second inputs to receive test EC bits from EC test nodes of the integrated circuit, and outputs to provide either the EC bits or the EC test bits to the memory in accordance with a test signal.
摘要翻译：具有该方法的集成电路包括存储器，该存储器包括多条存储器线，每条存储线包括多个用于存储数据位的数据单元，以及多个纠错（EC）单元，用于存储 EC位对应于存储在存储器线的数据单元中的数据位; EC输入电路，用于基于相应的数据位产生EC位; EC输出电路，包括EC校正电路，以根据从存储器线的EC单元读取的位来校正从每个存储器线的数据单元读取的位中的错误; 以及开关，其包括从EC输入电路接收EC位的第一输入，用于从集成电路的EC测试节点接收测试EC位的第二输入，以及向存储器中的EC位或EC测试位提供EC位或EC测试位按照测试信号。

7. 发明授权

US07984358B1 Error-correction memory architecture for testing production errors 有权
标题翻译：用于测试生产错误的纠错内存架构
公开(公告)号：US07984358B1
公开(公告)日：2011-07-19
申请号：US12352113
申请日：2009-01-12
申请人： Yosef Solt , Eitan Joshua
发明人： Yosef Solt , Eitan Joshua
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G06F11/2215 , G11C29/42 , G11C2029/0405
摘要： A system includes a first circuit generating error-correction (EC) bits based on test data. Memory comprises a plurality of memory lines each including a data portion storing the test data and an error-correction (EC) portion storing corresponding ones of the EC bits. An input receives the test data. A switching device selectively outputs one of the test data from the input and the EC bits and the test data from the first circuit to the memory. The test data comprise T pairs of test vectors. A first test vector of each of the T pairs of test vectors is an inverse of a second test vector of each of the T pairs of test vectors. Each of the first test vectors in the T pairs of test vectors is unique and each of the second test vectors in the T pairs of test vectors is unique. T is an integer greater than one.
摘要翻译：系统包括基于测试数据产生纠错（EC）位的第一电路。存储器包括多个存储线，每条存储线包括存储测试数据的数据部分和存储对应的EC位的纠错（EC）部分。输入接收测试数据。开关装置有选择地将来自输入端的测试数据和EC位和来自第一电路的测试数据中的一个输出到存储器。测试数据包括T对测试向量。 T对测试向量中的每一个的第一测试向量是每对T对测试向量的第二测试向量的倒数。 T对测试载体中的每个第一测试载体是唯一的，并且T对测试载体中的每个第二测试载体是唯一的。 T是大于1的整数。

8. 发明授权

US07478308B1 Error-correction memory architecture for testing production 有权
标题翻译：用于测试生产错误的纠错内存架构
公开(公告)号：US07478308B1
公开(公告)日：2009-01-13
申请号：US11787757
申请日：2007-04-17
申请人： Yosef Solt , Eitan Joshua
发明人： Yosef Solt , Eitan Joshua
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G06F11/2215 , G11C29/42 , G11C2029/0405
摘要： A system includes a first circuit that generates error-correction (EC) bits based on received data bits. Memory includes M data portions that store the data bits, where M is an integer greater than one, and M error-correction (EC) portions that store the EC bits. An input receives test data bits. A switching device selectively outputs one of the test data bits from the input and the EC and data bits from the first circuit to one of the M data portions and a corresponding one of the M EC portions. Vector pairs of the test data bits are stored in the memory. Bit values of an nth one of the vector pairs alternate every n bits. Vectors in the vector pairs are shifted n bits relative to each other, where n is an integer greater than zero.
摘要翻译：系统包括基于接收的数据位产生纠错（EC）位的第一电路。存储器包括存储数据位的M个数据部分，其中M是大于1的整数，以及存储EC位的M个纠错（EC）部分。输入接收测试数据位。开关装置有选择地将来自输入端的测试数据位之一和EC和数据位从第一电路输出到M个数据部分之一和M EC部分中的相应一个。测试数据位的矢量对存储在存储器中。第n个矢量对的位值每n位交替。向量对中的向量相对于彼此移位n位，其中n是大于零的整数。

9. 发明申请

US20080195901A1 OP-CODE BASED BUILT-IN-SELF-TEST 审中-公开
标题翻译：基于OP-CODE的内置内置测试
公开(公告)号：US20080195901A1
公开(公告)日：2008-08-14
申请号：US11969022
申请日：2008-01-03
申请人： Yosef Solt , Eitan Joshua
发明人： Yosef Solt , Eitan Joshua
IPC分类号： G11C29/12 , G06F11/26 , G06F11/22
CPC分类号： G11C29/16 , G11C29/46
摘要： A built-in-self-test (BIST) system for testing a memory that includes a scheduler module that generates a first test algorithm based on a set of operational codes. Each operational code defines a test operation to be performed by the first test algorithm on the memory. The BIST system also includes an execution module that applies the first test algorithm to the memory.
摘要翻译：内置自测（BIST）系统，用于测试包含基于一组操作代码生成第一测试算法的调度器模块的存储器。每个操作代码定义了由内存上的第一个测试算法执行的测试操作。 BIST系统还包括将第一测试算法应用于存储器的执行模块。

10. 发明授权

US07206988B1 Error-correction memory architecture for testing production errors 有权
标题翻译：用于测试生产错误的纠错内存架构
公开(公告)号：US07206988B1
公开(公告)日：2007-04-17
申请号：US11280892
申请日：2005-11-17
申请人： Yosef Solt , Eitan Joshua
发明人： Yosef Solt , Eitan Joshua
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G06F11/2215 , G11C29/42 , G11C2029/0405
摘要： An integrated circuit, having a method therefor, includes a memory including a plurality of memory lines, each memory line including a plurality of data cells each to store a data bit, and a plurality of error-correction (EC) cells each to store an EC bit corresponding to the data bits stored in the data cells of the memory line; an EC input circuit to generate the EC bits based on the corresponding data bits; an EC output circuit including an EC correction circuit to correct errors in the bits read from the data cells of each of the memory lines in accordance with the bits read from the EC cells of the memory line; and a switch including first inputs to receive the EC bits from the EC input circuit, second inputs to receive test EC bits from EC test nodes of the integrated circuit, and outputs to provide either the EC bits or the EC test bits to the memory in accordance with a test signal.
摘要翻译：具有该方法的集成电路包括存储器，该存储器包括多条存储器线，每条存储线包括多个用于存储数据位的数据单元，以及多个纠错（EC）单元，用于存储 EC位对应于存储在存储器线的数据单元中的数据位; EC输入电路，用于基于相应的数据位产生EC位; EC输出电路，包括EC校正电路，以根据从存储器线的EC单元读取的位来校正从每个存储器线的数据单元读取的位中的错误; 以及开关，其包括从EC输入电路接收EC位的第一输入，用于从集成电路的EC测试节点接收测试EC位的第二输入，以及向存储器中的EC位或EC测试位提供EC位或EC测试位按照测试信号。

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