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1. 发明授权

US06459133B1 Enhanced flux semiconductor device with mesa and method of manufacturing same 失效
标题翻译：具有台面的增强型通量半导体器件及其制造方法
公开(公告)号：US06459133B1
公开(公告)日：2002-10-01
申请号：US09545782
申请日：2000-04-07
申请人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Hendrik G. A. Huizing , Eddie Huang
发明人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Hendrik G. A. Huizing , Eddie Huang
IPC分类号： H01L2358
CPC分类号： H01L29/8618
摘要： The invention relates to a so-called punch-through diode with a mesa (12) comprising, in succession, a first (1), a second (2) and a third (3) semiconductor region (1) of, respectively, a first, a second and the first conductivity type, which punch-through diode is provided with two connection conductors (5, 6). During operation of said diode, a voltage is applied such that the second semiconductor region (2) is fully depleted. A drawback of the known punch-through diode resides in that the current flow is too large at lower voltages. In a punch-through diode according to the invention, a part (2A, 2B) of the second semiconductor region (2), which, viewed in projection, borders on the edge of the mesa (12), is provided with a larger flux of doping atoms of the second conductivity type than the remainder (2A) of the second semiconductor region (2). It has been found that the high current at a low voltage of the known diode is caused by the fact that the second semiconductor region (2) at the edge of the mesa (12) is depleted before the remainder of the second semiconductor region (2). By locally increasing the flux of doping atoms, the depletion at the edge is delayed as compared to the remainder of the second semiconductor region. Preferably, this result is obtained by locally increasing the thickness of the second semiconductor region (2). In this manner, a substantial current reduction at lower voltages is obtained in the diode in accordance with the invention.
摘要翻译：本发明涉及一种所谓的穿通二极管，其具有台面（12），它们分别包括第一（1），第二（2）和第三（3）半导体区域（1）第一和第二导电类型，该穿通二极管设置有两个连接导体（5,6）。在所述二极管的操作期间，施加电压使得第二半导体区域（2）完全耗尽。已知的穿通二极管的缺点在于电流在较低的电压下太大。在根据本发明的穿通二极管中，第二半导体区域（2）的一部分（2A，2B）在投影面上与台面（12）的边缘相邻地设置有较大的通量的第二导电类型的掺杂原子比第二半导体区域（2）的其余部分（2A）。已经发现，已知二极管的低电压下的高电流是由于在第二半导体区域（2）的剩余部分之前在台面（12）的边缘处的第二半导体区域（2）被耗尽的事实引起的，）。通过局部增加掺杂原子的通量，与第二半导体区域的剩余部分相比，边缘处的耗尽被延迟。优选地，通过局部增加第二半导体区域（2）的厚度来获得该结果。以这种方式，在根据本发明的二极管中获得在较低电压下的实质电流降低。

2. 发明授权

US06417526B2 Semiconductor device having a rectifying junction and method of manufacturing same 有权
标题翻译：具有整流结的半导体装置及其制造方法
公开(公告)号：US06417526B2
公开(公告)日：2002-07-09
申请号：US09288395
申请日：1999-04-08
申请人： Adam R. Brown , Godefridus A. M. Hurkx , Michael S. Peter , Hendrik G. A. Huizing , Wiebe B. De Boer
发明人： Adam R. Brown , Godefridus A. M. Hurkx , Michael S. Peter , Hendrik G. A. Huizing , Wiebe B. De Boer
IPC分类号： H01L29861
CPC分类号： H01L29/885 , H01L29/32 , Y10S438/979
摘要： The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly. In a device in accordance with the invention, the entire first region (1) comprises a mixed crystal of silicon and germanium, and the germanium content and the thickness of the first region (1) are selected so that the voltage built up in the semiconductor device remains below the level at which misfit dislocations develop. Surprisingly, it has been found that such a device can also be switched very rapidly, even more rapidly than the known device. The absence of misfit dislocations has an additional advantage, namely that the device is very reliable. Misfit dislocations do not develop if the product of said relative deviation in the lattice constant and the thickness of the first region is smaller than or equal to 40 nm %. A safe upper limit for said product is 30 nm %.
摘要翻译：本发明涉及一种半导体器件，其具有位于相反导电型的两个（半导体）区域（1,2）之间的整流结（5）。包括硅的第二区域（2）比第一区域（1）更厚并且具有更小的掺杂浓度，该第一区域包括包含硅和锗的混合晶体的子区域。两个区域（1,2）各自设置有连接导体（3,4）。这种装置可以非常适合地用作开关元件，特别是用作高电压和/或高功率的开关元件。在已知的器件中，硅 - 锗混晶被放宽，导致失配位错的形成。这些用于减少少数电荷载体的使用寿命，从而使装置能够非常快地切换。在根据本发明的装置中，整个第一区域（1）包括硅和锗的混合晶体，并且选择锗含量和第一区域（1）的厚度，使得在半导体中积聚的电压器件仍然低于发生错配位错的水平。令人惊讶的是，已经发现，这种装置也可以非常快速地切换，甚至比已知装置更快地切换。没有错配位错具有额外的优点，即该装置非常可靠。如果晶格常数相对偏差和第一区域的厚度的乘积小于或等于40nm％，则不会发生失配位错。所述产品的安全上限为30nm％。

3. 发明授权

US06436785B1 Method of manufacturing semiconductor device with a tunnel diode 有权
公开(公告)号：US06436785B1
公开(公告)日：2002-08-20
申请号：US09832724
申请日：2001-04-11
申请人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Jan W. Slotboom
发明人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Jan W. Slotboom
IPC分类号： H01L2120
摘要： A semiconductor device with a tunnel diode comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types having high enough doping concentrations to provide a tunneling junction. Portions (2A, 3A) of the semiconductor regions adjoining the junction comprise a mixed crystal of silicon and germanium. The doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions. The tunneling efficiency is substantially improved, and also because of the reduced bandgap of said portions (2A, 3A). A much steeper current-voltage characteristic both in the forward and in the reverse direction is achieved. Thus, the tunneling pn junction can be used as a transition between two conventional diodes which are stacked one on the other and formed in a single epitaxial growing process. The doping concentration may be 6×1019 or even more than 1020 at/cm3. A simple method of manufacturing such a device is preferably done at a temperature between 550° C. and 800° C.

4. 发明授权

US06242762B1 Semiconductor device with a tunnel diode and method of manufacturing same 失效
公开(公告)号：US06242762B1
公开(公告)日：2001-06-05
申请号：US09078231
申请日：1998-05-13
申请人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Jan W. Slotboom
发明人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Jan W. Slotboom
IPC分类号： H01L29861
CPC分类号： H01L29/885 , Y10S438/979
摘要： A semiconductor device with a tunnel diode (23) is particularly suitable for various applications. Such a device comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types and having doping concentrations which are so high that breakdown between them leads to conduction by means of tunnelling. A disadvantage of the known device is that the current-voltage characteristic is not yet steep enough for some applications. In a device according to the invention, the portions (2A, 3A) of the semiconductor regions (2, 3) adjoining the junction (23) comprise a mixed crystal of silicon and germanium. It is surprisingly found that the doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions (2, 3). The tunnelling efficiency is substantially improved as a result of this, and also because of the reduced bandgap of said portions (2A, 3A), and the device according to the invention has a much steeper current-voltage characteristic both in the forward and in the reverse direction. This opens perspectives for inter alia an attractive application where the tunnelling pn junction (23) is used as a transition between two conventional diodes, for example pn or pin diodes, which are used one stacked on the other and which can be formed in a single epitaxial growing process thanks to the invention. The portions (2A, 3A) adjoining the tunnelling junction (22) are preferably 5 to 30 nm thick and comprise between 10 and 50 at % germanium. The doping concentration may be 6×1019 or even more than 1020 at/cm3. The invention further relates to a simple method of manufacturing a device according to the invention. This is preferably done at a temperature of between 550° C. and 800° C.

5. 发明授权

US07660180B2 Dielectric antifuse for electro-thermally programmable device 有权
标题翻译：用于电热可编程器件的介质反熔丝
公开(公告)号：US07660180B2
公开(公告)日：2010-02-09
申请号：US11720320
申请日：2005-11-24
申请人： Hans M. B. Boeve , Karen Attenborough , Godefridus A. M. Hurkx , Prabhat Agarwal , Hendrik G. A. Huizing , Michael A. A. In'T Zandt , Jan W. Slotboom
发明人： Hans M. B. Boeve , Karen Attenborough , Godefridus A. M. Hurkx , Prabhat Agarwal , Hendrik G. A. Huizing , Michael A. A. In'T Zandt , Jan W. Slotboom
IPC分类号： G11C17/18
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.
摘要翻译：热可编程存储器具有可编程电阻的可编程电阻（20），优选地是相变材料的材料和位于可编程材料附近的吹制反熔丝（80）。这种吹制的反熔丝具有由导电层（90,110）包围的电介质层（100），以使得能够在制造期间在电介质两端施加短暂的高电压来吹动电介质中的小孔，以形成小导电路径，用作编程材料的微小电加热器。由于目前由孔的限制，为了切换到高电阻状态必须被加热的材料的体积非常小。因此，编程功率可能很低。

6. 发明授权

US06331467B1 Method of manufacturing a trench gate field effect semiconductor device 失效
标题翻译：制造沟槽栅场效应半导体器件的方法
公开(公告)号：US06331467B1
公开(公告)日：2001-12-18
申请号：US09538467
申请日：2000-03-29
申请人： Adam R. Brown , Raymond J. E. Hueting , Godefridus A. M. Hurkx
发明人： Adam R. Brown , Raymond J. E. Hueting , Godefridus A. M. Hurkx
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/165 , H01L29/66348 , H01L29/7397 , Y10S438/97
摘要： A semiconductor body (1) is provided having a first semiconductor region (3) of one conductivity type separated from a first major surface (5a) by a second semiconductor region (5) of the opposite conductivity type. A trench (7) is etched through the second semiconductor region (5) to an etch stop layer (4) provided in the region of the pn junction between the first (3) and second (5) regions, by using an etching process which enables the etching process to be stopped at the etch stop layer. A gate (8, 9) is provided within the trench (7). A source (12) separated from the first region (3) by the second region (5) is formed adjacent the trench so that a conduction channel area (50) of the second region (5) adjacent the trench provides a conduction path between the source and first regions which is controllable by the gate.
摘要翻译：半导体本体（1）具有通过相反导电类型的第二半导体区域（5）与第一主表面（5a）分离的一种导电类型的第一半导体区域（3）。通过使用蚀刻工艺将沟槽（7）通过第二半导体区域（5）蚀刻到设置在第一（3）和第二（5）区域之间的pn结区域中的蚀刻停止层（4），其中使蚀刻工艺在蚀刻停止层处停止。在沟槽（7）内设有一个门（8,9）。与沟槽相邻地形成与第一区域（3）分离的源极（12），使得邻近沟槽的第二区域（5）的导电通道区域（50）提供在第二区域源极和第一区域，其可由栅极控制。

7. 发明申请

US20120038415A1 METHOD AND APPARATUS FOR MAINTAINING CIRCUIT STABILITY 有权
标题翻译：维持电路稳定性的方法和装置
公开(公告)号：US20120038415A1
公开(公告)日：2012-02-16
申请号：US13202922
申请日：2010-01-21
申请人： Tony Vanhoucke , Godefridus A. M. Hurkx
发明人： Tony Vanhoucke , Godefridus A. M. Hurkx
IPC分类号： G05F1/10 , G06F19/00
CPC分类号： H03F1/52 , H03F2200/447 , H03F2200/462 , H03F2200/468 , H03F2200/471
摘要： A control circuit for a transistor arrangement comprises a monitoring arrangement (60) for monitoring the current flow and voltage across the transistor arrangement (50) and means (62) for determining if the current and voltage values define an operating point which falls within a stable operating region. The stable operating region comprises a region having a boundary (30) which comprises an electro-thermal instability line.
摘要翻译：一种用于晶体管装置的控制电路包括用于监测晶体管装置（50）两端的电流和电压的监视装置（60）和用于确定电流和电压值是否限定了稳定的工作点的装置（62）经营区域。稳定工作区域包括具有包括电热不稳定线的边界（30）的区域。

8. 发明授权

US06605862B2 Trench semiconductor devices 失效
标题翻译：沟槽半导体器件
公开(公告)号：US06605862B2
公开(公告)日：2003-08-12
申请号：US10068921
申请日：2002-02-07
申请人： Rob Van Dalen , Christelle Rochefort , Godefridus A. M. Hurkx
发明人： Rob Van Dalen , Christelle Rochefort , Godefridus A. M. Hurkx
IPC分类号： H01L29414
CPC分类号： H01L29/405 , H01L29/408 , H01L29/41766 , H01L29/7802 , H01L29/7813 , H01L29/861
摘要： A semiconductor device, such as a MOSFET or PN diode rectifier, has a p-n junction (24) between a first device region (23) and an underlying voltage-sustaining zone (20). Trenched field-shaping regions (40) extend through the voltage-sustaining zone (20) to improve the voltage-blocking and on-resistance characteristics of the device. The trenched field-shaping region (40) comprises a resistive path (42) accommodated in a trench (41) that has an insulating layer (44) at its side-walls. The insulating layer (44) dielectrically couples potential from the resistive path (42) to the voltage-sustaining zone (20) that is depleted in a voltage-blocking mode of operation of the device. The insulating layer (44) extends at the side-walls of the trench (41) to an upper level (81) that is higher than a lower level (82) at which the resistive path (42) starts in the trench (41). This lower level (82) is more closely aligned to the p-n junction (24) and is protected by the insulating layer (44) extending to the higher level (81). This construction enables the electric field distribution in the voltage-sustaining zone (20) to be improved by aligning very closely the start of the potential drop along the resistive path (42) with the p-n junction depth (d).
摘要翻译：诸如MOSFET或PN二极管整流器的半导体器件在第一器件区域（23）和下伏电压维持区（20）之间具有p-n结（24）。倾斜的场成形区域（40）延伸通过电压维持区域（20），以改善装置的压阻和导通电阻特性。沟槽场整形区域（40）包括容纳在其侧壁上具有绝缘层（44）的沟槽（41）中的电阻路径（42）。绝缘层（44）将电阻从电阻路径（42）介电地耦合到耗尽该器件的电压阻断模式的电压维持区（20）。绝缘层（44）在沟槽（41）的侧壁处延伸到高于电阻路径（42）在沟槽（41）中开始的较低电平（82）的上电平（81）。该较低电平（82）与p-n结（24）更紧密地对准，并被延伸到较高电平（81）的绝缘层（44）保护。这种结构使得能够通过非常接近地沿着电阻路径（42）与p-n结深度（d）非常接近的电位降的起始来提高电压维持区（20）中的电场分布。

9. 发明授权

US08319546B2 Method and apparatus for maintaining circuit stability 有权
标题翻译：保持电路稳定性的方法和装置
公开(公告)号：US08319546B2
公开(公告)日：2012-11-27
申请号：US13202922
申请日：2010-01-21
申请人： Tony Vanhoucke , Godefridus A. M. Hurkx
发明人： Tony Vanhoucke , Godefridus A. M. Hurkx
IPC分类号： G05F1/10 , G05F3/02 , H03K17/04
CPC分类号： H03F1/52 , H03F2200/447 , H03F2200/462 , H03F2200/468 , H03F2200/471
摘要： A control circuit for a transistor arrangement comprises a monitoring arrangement (60) for monitoring the current flow and voltage across the transistor arrangement (50) and means (62) for determining if the current and voltage values define an operating point which falls within a stable operating region. The stable operating region comprises a region having a boundary (30) which comprises an electro-thermal instability line.
摘要翻译：一种用于晶体管装置的控制电路包括用于监测晶体管装置（50）两端的电流和电压的监视装置（60）和用于确定电流和电压值是否限定了稳定的工作点的装置（62）经营区域。稳定工作区域包括具有包括电热不稳定线的边界（30）的区域。

10. 发明授权

US07839209B2 Tunnel field effect transistor 有权
标题翻译：隧道场效应晶体管
公开(公告)号：US07839209B2
公开(公告)日：2010-11-23
申请号：US12444140
申请日：2007-10-03
申请人： Gilberto Curatola , Prabhat Agarwal , Jan W. Slotboom , Godefridus A. M. Hurkx , Radu Surdeanu , Gerben Doornbos
发明人： Gilberto Curatola , Prabhat Agarwal , Jan W. Slotboom , Godefridus A. M. Hurkx , Radu Surdeanu , Gerben Doornbos
IPC分类号： H01L25/00
CPC分类号： H01L29/161 , H01L29/165 , H01L29/7391
摘要： A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).
摘要翻译：隧道晶体管包括与漏扩散（6）相反的导电类型的源极扩散（4），使得在较低掺杂区域（8）中的源极和漏极扩散之间形成耗尽层。绝缘栅极（16）控制耗尽层的位置和厚度。该装置包括形成在由下层（2）和盖层（22）的不同材料制成的聚集层（20）中的量子阱。

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