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1. 发明申请

US20130009277A1 STRUCTURE AND METHOD FOR FORMING ISOLATION AND BURIED PLATE FOR TRENCH CAPACITOR 有权
标题翻译：用于形成用于TRENCH电容器的隔离和平板的结构和方法
公开(公告)号：US20130009277A1
公开(公告)日：2013-01-10
申请号：US13617576
申请日：2012-09-14
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/06
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

2. 发明授权

US08298908B2 Structure and method for forming isolation and buried plate for trench capacitor 有权
标题翻译：用于形成沟槽电容器的隔离和掩埋板的结构和方法
公开(公告)号：US08298908B2
公开(公告)日：2012-10-30
申请号：US12704084
申请日：2010-02-11
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

3. 发明申请

US20110193193A1 STRUCTURE AND METHOD FOR FORMING ISOLATION AND BURIED PLATE FOR TRENCH CAPACITOR 有权
标题翻译：用于形成用于TRENCH电容器的隔离和平板的结构和方法
公开(公告)号：US20110193193A1
公开(公告)日：2011-08-11
申请号：US12704084
申请日：2010-02-11
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

4. 发明授权

US08637958B2 Structure and method for forming isolation and buried plate for trench capacitor 有权
标题翻译：用于形成沟槽电容器的隔离和掩埋板的结构和方法
公开(公告)号：US08637958B2
公开(公告)日：2014-01-28
申请号：US13617576
申请日：2012-09-14
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

5. 发明授权

US08354675B2 Enhanced capacitance deep trench capacitor for EDRAM 有权
标题翻译： EDRAM增强型电容深沟槽电容器
公开(公告)号：US08354675B2
公开(公告)日：2013-01-15
申请号：US12775532
申请日：2010-05-07
申请人： Oh-jung Kwon , Junedong Lee , Chengwen Pei , Geng Wang
发明人： Oh-jung Kwon , Junedong Lee , Chengwen Pei , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L28/82 , H01L27/10867 , H01L29/66181
摘要： A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.
摘要翻译：提供了包括手柄衬底，可选的下绝缘体层，掺杂多晶半导体层，上绝缘体层和顶部半导体层的衬底的衬底。通过顶部半导体层，上部绝缘体层和掺杂多晶半导体层形成深沟槽。多晶半导体层的暴露的垂直表面被晶体学蚀刻以在深沟槽中形成随机刻面，从而增加深沟槽中的多晶半导体层的总暴露表面积。沉积节点电介质和至少一种导电材料以填充沟槽并形成构成eDRAM的电容器的掩埋带部分。可以形成存取晶体管和其它逻辑器件。

6. 发明申请

US20110272702A1 ENHANCED CAPACITANCE DEEP TRENCH CAPACITOR FOR EDRAM 有权
标题翻译： EDRAM的增强电容深度电容器
公开(公告)号：US20110272702A1
公开(公告)日：2011-11-10
申请号：US12775532
申请日：2010-05-07
申请人： Oh-jung Kwon , Junedong Lee , Chengwen Pei , Geng Wang
发明人： Oh-jung Kwon , Junedong Lee , Chengwen Pei , Geng Wang
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L28/82 , H01L27/10867 , H01L29/66181
摘要： A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.
摘要翻译：提供了包括手柄衬底，可选的下绝缘体层，掺杂多晶半导体层，上绝缘体层和顶部半导体层的衬底的衬底。通过顶部半导体层，上部绝缘体层和掺杂多晶半导体层形成深沟槽。多晶半导体层的暴露的垂直表面被晶体学蚀刻以在深沟槽中形成随机刻面，从而增加深沟槽中的多晶半导体层的总暴露表面积。沉积节点电介质和至少一种导电材料以填充沟槽并形成构成eDRAM的电容器的掩埋带部分。可以形成存取晶体管和其它逻辑器件。

7. 发明授权

US08691697B2 Self-aligned devices and methods of manufacture 失效
标题翻译：自对准装置和制造方法
公开(公告)号：US08691697B2
公开(公告)日：2014-04-08
申请号：US12943956
申请日：2010-11-11
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L21/31056 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.
摘要翻译：一种方法包括在具有预定间距的基底上形成图案线。该方法还包括在图案化线的侧壁上形成间隔壁。该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。该方法还包括将图案化线和另一图案化线的图案转移到衬底。

8. 发明授权

US08575670B2 Embedded dynamic random access memory device formed in an extremely thin semiconductor on insulator (ETSOI) substrate 有权
标题翻译：在非常薄的半导体绝缘体（ETSOI）衬底上形成的嵌入式动态随机存取存储器件
公开(公告)号：US08575670B2
公开(公告)日：2013-11-05
申请号：US13316056
申请日：2011-12-09
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/10861 , H01L28/91 , H01L29/945
摘要： A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.
摘要翻译：一种存储器件，包括具有厚度小于30nm的掩埋介电层的SOI衬底，以及穿过SOI层的延伸沟槽和埋入电介质层到SOI衬底的基底半导体层中的沟槽。电容器存在于沟槽的下部。电介质垫片存在于沟槽上部的侧壁上。介质间隔物存在于沟槽的部分，其中侧壁由SOI层和埋入的介电层提供。导电材料填充物存在于沟槽的上部。半导体器件存在于与沟槽相邻的SOI层上。半导体器件通过导电材料填充与电容器电连通。

9. 发明授权

US09048339B2 Deep trench capacitor 有权
标题翻译：深沟槽电容器
公开(公告)号：US09048339B2
公开(公告)日：2015-06-02
申请号：US13606448
申请日：2012-09-07
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/84 , H01L29/66 , H01L27/108 , H01L27/12
CPC分类号： H01L28/60 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.
摘要翻译：提供了在绝缘体上半导体衬底中形成深沟槽电容器的方法。该方法可以包括提供定位在大块衬底之上的衬垫层，将深沟槽蚀刻到衬垫层中，以及从衬垫层的顶表面延伸到体衬底内的位置的本体衬底，以及掺杂散装衬底形成掩埋板。该方法还包括沉积基本上填充深沟槽的节点电介质，内部电极和电介质帽，节点电介质位于掩埋板和内部电极之间，电介质帽位于深沟槽的顶部，去除衬垫层，在本体衬底的顶部上生长绝缘体层，以及在绝缘体层的顶部上生长绝缘体上半导体层。

10. 发明授权

US08936996B2 Structure and method for topography free SOI integration 有权
标题翻译：地形自由SOI集成的结构和方法
公开(公告)号：US08936996B2
公开(公告)日：2015-01-20
申请号：US12958429
申请日：2010-12-02
申请人： Ravi M. Todi , Joseph Ervin , Chengwen Pei , Geng Wang
发明人： Ravi M. Todi , Joseph Ervin , Chengwen Pei , Geng Wang
IPC分类号： H01L21/76 , H01L29/02 , H01L21/762
CPC分类号： H01L29/02 , H01L21/76254
摘要： A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.
摘要翻译：提供了包括具有特征的半导体氧化物层的半导体结构。具有特征的半导体氧化物层位于有源半导体层和手柄基板之间。半导体结构包括有源半导体层的平坦化顶表面，使得半导体氧化物层位于平坦化的顶表面之下。半导体氧化物层内的特征与有源半导体层的表面配合。

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