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1. 发明申请

US20060227917A1 High-speed serial data transceiver and related methods 有权
公开(公告)号：US20060227917A1
公开(公告)日：2006-10-12
申请号：US11446144
申请日：2006-06-05
申请人： Aaron Buchwald , Michael Le , Josephus Van Engelen , Xicheng Jiang , Hui Wang , Howard Baumer , Avanindra Madisetti
发明人： Aaron Buchwald , Michael Le , Josephus Van Engelen , Xicheng Jiang , Hui Wang , Howard Baumer , Avanindra Madisetti
IPC分类号： H04L7/00
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

2. 发明授权

US08223828B2 Methods and systems for adaptive receiver equalization 有权
标题翻译：自适应接收机均衡的方法和系统
公开(公告)号：US08223828B2
公开(公告)日：2012-07-17
申请号：US11976185
申请日：2007-10-22
申请人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discrete-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.
摘要翻译：用于最小化模拟数据信号中的失真的方法和系统包括在接收端均衡模拟数据信号。在一个实施例中，本发明使均衡参数适应于与模拟数据信号相关联的信号路径。自适应控制逻辑由模拟和/或数字组件实现。在一个实施例中，本发明使模拟数据信号的离散时间模拟表示相等。在一个实施例中，本发明数字地控制均衡参数。在一个实施例中，所得到的均衡的模拟数据信号被数字化。在示例实现中，对模拟数据信号进行采样，测量样本的质量，并且根据需要使用数字控制来调整一个或多个均衡参数以最小化样本的失真。然后将均衡的样品数字化。本发明适用于低速模拟数据信号和多吉比特数据速率模拟信号。

3. 发明授权

US07286597B2 Methods and systems for adaptive receiver equalization 失效
标题翻译：自适应接收机均衡的方法和系统
公开(公告)号：US07286597B2
公开(公告)日：2007-10-23
申请号：US09844283
申请日：2001-04-30
申请人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.
摘要翻译：用于最小化模拟数据信号中的失真的方法和系统包括在接收端均衡模拟数据信号。在一个实施例中，本发明使均衡参数适应于与模拟数据信号相关联的信号路径。自适应控制逻辑由模拟和/或数字组件实现。在一个实施例中，本发明均衡模拟数据信号的谨慎时间模拟表示。在一个实施例中，本发明数字地控制均衡参数。在一个实施例中，所得到的均衡的模拟数据信号被数字化。在示例实现中，对模拟数据信号进行采样，测量样本的质量，并且根据需要使用数字控制来调整一个或多个均衡参数以最小化样本的失真。然后将均衡的样品数字化。本发明适用于低速模拟数据信号和多吉比特数据速率模拟信号。

4. 发明授权

US08472512B2 Methods and systems for adaptive receiver equalization 有权
标题翻译：自适应接收机均衡的方法和系统
公开(公告)号：US08472512B2
公开(公告)日：2013-06-25
申请号：US13467531
申请日：2012-05-09
申请人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： Methods and systems for adaptively equalizing an analog information signal for a signal path, including sampling the analog information signal, thereby generating analog samples, and performing an equalizing process on the analog samples, wherein the equalizing includes processing an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples to produce equalized analog samples.
摘要翻译：用于自适应地均衡用于信号路径的模拟信息信号的方法和系统，包括对模拟信息信号进行采样，从而产生模拟采样，并对模拟采样进行均衡处理，其中均衡包括处理平均过渡后样本幅度以及模拟样本的稳态样本幅度的平均值，以产生均衡的模拟样本。

5. 发明申请

US20120243598A1 Methods and Systems for Adaptive Receiver Equalization 有权
标题翻译：自适应接收机均衡的方法和系统
公开(公告)号：US20120243598A1
公开(公告)日：2012-09-27
申请号：US13467531
申请日：2012-05-09
申请人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03H7/00
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： Methods and systems for adaptively equalizing an analog information signal for a signal path, including sampling the analog information signal, thereby generating analog samples, and performing an equalizing process on the analog samples, wherein the equalizing includes processing an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples to produce equalized analog samples.
摘要翻译：用于自适应地均衡用于信号路径的模拟信息信号的方法和系统，包括对模拟信息信号进行采样，从而产生模拟采样，并对模拟采样进行均衡处理，其中均衡包括处理平均过渡后样本幅度以及模拟样本的稳态样本幅度的平均值，以产生均衡的模拟样本。

6. 发明申请

US20080117963A1 Methods and systems for adaptive receiver equalization 有权
标题翻译：自适应接收机均衡的方法和系统
公开(公告)号：US20080117963A1
公开(公告)日：2008-05-22
申请号：US11976185
申请日：2007-10-22
申请人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.
摘要翻译：用于最小化模拟数据信号中的失真的方法和系统包括在接收端均衡模拟数据信号。在一个实施例中，本发明使均衡参数适应于与模拟数据信号相关联的信号路径。自适应控制逻辑由模拟和/或数字组件实现。在一个实施例中，本发明均衡模拟数据信号的谨慎时间模拟表示。在一个实施例中，本发明数字地控制均衡参数。在一个实施例中，所得到的均衡的模拟数据信号被数字化。在示例实现中，对模拟数据信号进行采样，测量样本的质量，并且根据需要使用数字控制来调整一个或多个均衡参数以最小化样本的失真。然后将均衡的样品数字化。本发明适用于低速模拟数据信号和多吉比特数据速率模拟信号。

7. 发明申请

US20050286669A1 Phase interpolator based transmission clock control 失效
标题翻译：基于相位插值器的传输时钟控制
公开(公告)号：US20050286669A1
公开(公告)日：2005-12-29
申请号：US10876602
申请日：2004-06-28
申请人： Aaron Buchwald , Michael Le , Hui Wang , Howard Baumer , Pieter Vorenkamp
发明人： Aaron Buchwald , Michael Le , Hui Wang , Howard Baumer , Pieter Vorenkamp
IPC分类号： H04L7/00 , H04L25/20
CPC分类号： H04L7/0091 , H04L7/0025 , H04L7/0029 , H04L25/20
摘要： A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled to a master timing generator and a transmission module. The phase interpolator is also coupled to a receiver interpolator control module and/or an external interpolator control module. When the system is operating in repeat mode, the transmitter phase interpolator receives a control signal from a receiver interpolator control module. The transmitter phase interpolator uses the signal to synchronize the transmission clock to the sampling clock. When the system is operating in test mode, a user defines a transmission data profile in an external interpolator control module. The external interpolator control module generates a control signal based on the profile. The transmitter phase interpolator uses the signal to generate a transmission clock that is used by the transmission module to generate a data stream having the desired profile.
摘要翻译：提供了一种用于基于相位插值器的传输时钟控制的系统和方法。该系统包括具有耦合到主定时发生器和传输模块的相位插值器的发射机。相位插值器还耦合到接收器插值器控制模块和/或外部插值器控制模块。当系统以重复模式运行时，发射机相位插值器从接收器插值器控制模块接收控制信号。发射机相位内插器使用信号将传输时钟同步到采样时钟。当系统在测试模式下操作时，用户在外部插值器控制模块中定义传输数据简档。外部内插器控制模块基于轮廓生成控制信号。发射机相位内插器使用该信号来生成传输模块使用的传输时钟，以生成具有所需简档的数据流。

8. 发明授权

US07450050B2 Switched-capacitor reset architecture for opamp 有权
标题翻译：开关电容复位架构
公开(公告)号：US07450050B2
公开(公告)日：2008-11-11
申请号：US11732901
申请日：2007-04-05
申请人： Afshin Rezayee , Ken Martin , Aaron Buchwald
发明人： Afshin Rezayee , Ken Martin , Aaron Buchwald
IPC分类号： H03M1/38
CPC分类号： H03M1/1023 , H03F3/005 , H03M1/0695 , H03M1/442
摘要： An analog digital converter with switched-capacitor reset architecture. The analog to digital converter (ADC) includes a plurality of pipelined stages, each stage including an analog to digital converter comprising a pair of comparators outputting signals to a multiplying digital to analog converter (MDAC). The MDAC includes an opamp and a reset circuit connected to inputs of the opamp, the reset circuit including first and second capacitors and switching circuitry for precharging each of the first and second capacitors to a difference between the input and output common-mode voltages of the opamp, and during a reset phase of the MDAC, connecting the first capacitor between a positive input and a negative output of the opamp and connecting the second capacitor between a negative input and a positive output of the opamp to reset the opamp.
摘要翻译：具有开关电容复位架构的模拟数字转换器。模数转换器（ADC）包括多个流水线级，每级包括一个模数转换器，包括一对比较器，输出信号到乘法数模转换器（MDAC）。 MDAC包括连接到运算放大器的输入的运算放大器和复位电路，复位电路包括第一和第二电容器以及用于将第一和第二电容器中的每一个预充电到第一和第二电容器的输入和输出共模电压之间的差的开关电路并且在MDAC的复位阶段期间，将第一电容器连接到运算放大器的正输入和负输出之间，并将第二电容器连接到运算放大器的负输入和正输出之间，以重置运算放大器。

9. 发明授权

US07586987B2 High speed data link with transmitter equalization and receiver equalization 有权
标题翻译：具有发射机均衡和接收机均衡的高速数据链路
公开(公告)号：US07586987B2
公开(公告)日：2009-09-08
申请号：US10680490
申请日：2003-10-08
申请人： Pieter Vorenkamp , Aaron Buchwald
发明人： Pieter Vorenkamp , Aaron Buchwald
IPC分类号： H04B3/00 , H04L25/03
CPC分类号： H04L25/03878 , H04B3/144
摘要： A high speed data link includes transmitter equalization and (passive) receiver equalization to compensate for frequency distortion of the data link. In one embodiment, the transmitter equalization is performed with a de-emphasis circuit. The transmitter de-emphasis circuit pre-distorts an input signal to compensate for at least some of the frequency distortion in the data caused by the transmission line. The (passive) receive equalization circuit further compensates for the frequency distortion at the output of the transmission line to flatten the amplitude response of the output signal, and thereby reduce inter-symbol interference, improve media reach and improve the bit error rate (BER).
摘要翻译：高速数据链路包括发射机均衡和（无源）接收机均衡以补偿数据链路的频率失真。在一个实施例中，用去加重电路来执行发射机均衡。发射机去加重电路预失真输入信号，以补偿由传输线引起的数据中的至少一些频率失真。（无源）接收均衡电路进一步补偿传输线输出端的频率失真，使输出信号的振幅响应平坦化，从而减少符号间干扰，提高媒体距离，提高误码率（BER）。

10. 发明申请

US20070247348A1 Switched-capacitor reset architecture for opamp 有权
标题翻译：开关电容复位架构
公开(公告)号：US20070247348A1
公开(公告)日：2007-10-25
申请号：US11732901
申请日：2007-04-05
申请人： Afshin Rezayee , Ken Martin , Aaron Buchwald
发明人： Afshin Rezayee , Ken Martin , Aaron Buchwald
IPC分类号： H03M1/38
CPC分类号： H03M1/1023 , H03F3/005 , H03M1/0695 , H03M1/442
摘要： An analog digital converter with switched-capacitor reset architecture. The analog to digital converter (ADC) includes a plurality of pipelined stages, each stage including an analog to digital converter comprising a pair of comparators outputting signals to a multiplying digital to analog converter (MDAC). The MDAC includes an opamp and a reset circuit connected to inputs of the opamp, the reset circuit including first and second capacitors and switching circuitry for precharging each of the first and second capacitors to a difference between the input and output common-mode voltages of the opamp, and during a reset phase of the MDAC, connecting the first capacitor between a positive input and a negative output of the opamp and connecting the second capacitor between a negative input and a positive output of the opamp to reset the opamp.
摘要翻译：具有开关电容复位架构的模拟数字转换器。模数转换器（ADC）包括多个流水线级，每级包括一个模数转换器，包括一对比较器，输出信号到乘法数模转换器（MDAC）。 MDAC包括连接到运算放大器的输入的运算放大器和复位电路，复位电路包括第一和第二电容器以及用于将第一和第二电容器中的每一个预充电到第一和第二电容器的输入和输出共模电压之间的差的开关电路并且在MDAC的复位阶段期间，将第一电容器连接到运算放大器的正输入和负输出之间，并将第二电容器连接到运算放大器的负输入和正输出之间，以重置运算放大器。

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