专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08321169B2 Method and system for compensating temperature readings from a temperature sensing crystal integrated circuit 有权
标题翻译：用于补偿温度感应晶体集成电路的温度读数的方法和系统
公开(公告)号：US08321169B2
公开(公告)日：2012-11-27
申请号：US13085407
申请日：2011-04-12
申请人： Todd Brooks , Vinay Chandrasekhar , Josephus Van Engelen , Jared Welz
发明人： Todd Brooks , Vinay Chandrasekhar , Josephus Van Engelen , Jared Welz
IPC分类号： G01K15/00 , G06F19/00
CPC分类号： G01R19/2506 , G01K7/32
摘要： Aspects of a method and system for compensating temperature readings from a temperature sensing crystal integrated circuit are provided. An electronic device may digitize a temperature indication received from a temperature sensing circuit, digitize one or more calibration voltages received from said temperature sensing circuit, and calculate a compensated temperature indication utilizing the digitized calibration voltage(s), and the digitized temperature indication, and data from a table that characterizes behavior of the temperature sensing circuit as a function of temperature. One or more circuits in the electronic device may be controlled based on the compensated temperature indication. The compensated temperature indication may compensate for a gain error and/or offset error of a digital to analog converter that digitizes the temperature indication and the calibration voltage(s). There may be two calibration voltages.
摘要翻译：提供了用于补偿来自温度感测晶体集成电路的温度读数的方法和系统的方面。电子设备可以数字化从温度检测电路接收的温度指示，数字化从所述温度检测电路接收的一个或多个校准电压，并且使用数字化校准电压和数字化温度指示来计算补偿温度指示，以及来自表格的数据表示温度感测电路的行为作为温度的函数。可以基于补偿的温度指示来控制电子设备中的一个或多个电路。补偿温度指示可以补偿数字化温度指示和校准电压的数模转换器的增益误差和/或偏移误差。可能有两个校准电压。

2. 发明授权

US08201995B2 Method and system for a temperature sensing crystal integrated circuit with digital temperature output 有权
标题翻译：具有数字温度输出的温度感应晶体集成电路的方法和系统
公开(公告)号：US08201995B2
公开(公告)日：2012-06-19
申请号：US12364064
申请日：2009-02-02
申请人： Evan McCarthy , John Walley , Todd L Brooks , Vinay Chandrasekhar , Josephus Van Engelen , Jared Welz
发明人： Evan McCarthy , John Walley , Todd L Brooks , Vinay Chandrasekhar , Josephus Van Engelen , Jared Welz
IPC分类号： H03L1/00
CPC分类号： G01R19/2506 , G01K7/32
摘要： Aspects of a method and system for a temperature sensing crystal Integrated circuit with digital temperature output are provided. In this regard, an indication of temperature may be generated in an integrated circuit (IC) comprising a memory, a crystal or crystal oscillator, and at least a portion of an analog-to-digital converter. The temperature indication may be digitized via the analog-to-digital converter. Operation of one or more circuits may be controlled based on the digital temperature indication. The digital temperature indication may be communicated over a communication bus. An analog portion of the analog-to-digital converter may be integrated in the IC and may comprise, for example, a delta-sigma modulator. A digital portion of the analog-to-digital converter may be external to the IC and may comprise, for example, a digital filter.
摘要翻译：提供了一种温度感应晶体的方法和系统。具有数字温度输出的集成电路。在这方面，可以在包括存储器，晶体或晶体振荡器的集成电路（IC）以及模数转换器的至少一部分中产生温度指示。温度指示可以通过模拟 - 数字转换器进行数字化。可以基于数字温度指示来控制一个或多个电路的操作。数字温度指示可以通过通信总线传送。模数转换器的模拟部分可以集成在IC中，并且可以包括例如Δ-Σ调制器。模数转换器的数字部分可以在IC的外部，并且可以包括例如数字滤波器。

3. 发明申请

US20060166715A1 Integrated and detachable wireless headset element for cellular/mobile/portable phones and audio playback devices 有权
公开(公告)号：US20060166715A1
公开(公告)日：2006-07-27
申请号：US11120455
申请日：2005-05-03
申请人： Josephus Van Engelen , Jeyhan Karaoguz , Nambirajan Seshadri , James Bennett
发明人： Josephus Van Engelen , Jeyhan Karaoguz , Nambirajan Seshadri , James Bennett
IPC分类号： H04M1/00
CPC分类号： H04M1/6066 , H04M1/0256 , H04M1/6033 , H04M1/725 , H04M2250/02
摘要： A modular wireless headset having integrated but detachable elements is operable to service a cellular wireless terminal, streamed media or playback device. This modular wireless headset may include a wireless microphone and a wireless earpiece. The wireless earpiece may physically couple to the wireless microphone and a base unit in order to exchange information and share power resources. A power distribution controller allocates power between the wireless earpiece, wireless microphone, and base unit when physically coupled to operate or charge internal power supplies of the components.

4. 发明申请

US20050248406A1 System to accelerate settling of an amplifier 有权
标题翻译：用于加速放大器稳定的系统
公开(公告)号：US20050248406A1
公开(公告)日：2005-11-10
申请号：US11182972
申请日：2005-07-18
申请人： Josephus van Engelen , Kwang Kim , Mark Chambers
发明人： Josephus van Engelen , Kwang Kim , Mark Chambers
IPC分类号： H03F3/45
CPC分类号： H03F3/45659 , H03F2203/45401 , H03F2203/45431 , H03F2203/45432
摘要： A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches steady-state within a specified time period from stand-by or another state without using more current than is needed for steady-state. A comparator in a common-mode feedback system compares a desired amplifier output signal to one or more nodes of the amplifier. A result of the comparison is compared to a threshold value using a comparator in a settling acceleration system. If the result crosses the threshold, a controller turns on a driver in the settling acceleration system. The driver pulls on one or more nodes of the amplifier, which, along with a driver in the amplifier system pulling on the node, quickly brings the amplifier to settling or steady state.
摘要翻译：系统和方法用于加速放大器系统中放大器的稳定状态或稳态。这用于确保放大器在待机或其他状态的指定时间段内达到稳态，而不需要比稳态所需的电流更多的电流。共模反馈系统中的比较器将期望的放大器输出信号与放大器的一个或多个节点进行比较。比较结果与使用稳定加速系统中的比较器的阈值进行比较。如果结果超过阈值，控制器将在稳定加速系统中打开驱动程序。驱动器拉动放大器的一个或多个节点，其中拉动节点的放大器系统中的驱动器快速使放大器稳定或稳定。

5. 发明申请

US20050046481A1 System and method to accelerate settling of an amplifier 有权
公开(公告)号：US20050046481A1
公开(公告)日：2005-03-03
申请号：US10653348
申请日：2003-09-03
申请人： Josephus van Engelen , Kwang Kim , Mark Chambers
发明人： Josephus van Engelen , Kwang Kim , Mark Chambers
IPC分类号： H03F3/45
CPC分类号： H03F3/45659 , H03F2203/45401 , H03F2203/45431 , H03F2203/45432
摘要： A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches steady-state within a specified time period from stand-by or another state without using more current than is needed for steady-state. A comparator in a common-mode feedback system compares a desired amplifier output signal to one or more nodes of the amplifier. A result of the comparison is compared to a threshold value using a comparator in a settling acceleration system. If the result crosses the threshold, a controller turns on a driver in the settling acceleration system. The driver pulls on one or more nodes of the amplifier, which, along with a driver in the amplifier system pulling on the node, quickly brings the amplifier to settling or steady state.

6. 发明申请

US20070194836A1 Precharged power-down biasing circuit 失效
标题翻译：预充电掉电偏置电路
公开(公告)号：US20070194836A1
公开(公告)日：2007-08-23
申请号：US11785216
申请日：2007-04-16
申请人： Kwang Kim , Josephus van Engelen
发明人： Kwang Kim , Josephus van Engelen
IPC分类号： G05F1/10
CPC分类号： H04W52/028 , Y02D70/142
摘要： A power-down biasing circuit includes a current source connected to a drain of a first NMOS transistor through a first switch. A gate of the first NMOS transistor is connected to the current source, and a source of the first NMOS transistor is connected to ground. A first pre-chargeable capacitor is connected between the gate of the first NMOS transistor and ground. A plurality of NMOS transistors form a current multiplier and have gates connected to the current reference. A plurality of current mirrors are connected to drains of the plurality of NMOS transistors and to output switches. Each current mirror has a first PMOS transistor whose drain is connected to a drain of a corresponding one of the plurality of NMOS transistors through a second switch, whose gate is connected to the drain of the corresponding one of the plurality of NMOS transistors and whose source is connected to a supply voltage; a second capacitor is connected between the gate of the first PMOS transistor and the supply voltage; and at least two PMOS transistors are connected as a current multiplier to the output switches. Cascode equivalent biasing circuits are described also.
摘要翻译：掉电偏置电路包括通过第一开关连接到第一NMOS晶体管的漏极的电流源。第一NMOS晶体管的栅极连接到电流源，并且第一NMOS晶体管的源极连接到地。第一可预充电电容器连接在第一NMOS晶体管的栅极和地之间。多个NMOS晶体管形成电流倍增器并且具有连接到电流基准的栅极。多个电流镜连接到多个NMOS晶体管的漏极和输出开关。每个电流镜具有第一PMOS晶体管，其漏极通过第二开关连接到多个NMOS晶体管中相应的一个NMOS晶体管的漏极，第二开关的栅极连接到多个NMOS晶体管中对应的一个NMOS晶体管的漏极，连接到电源电压; 第二电容器连接在第一PMOS晶体管的栅极和电源电压之间; 并且至少两个PMOS晶体管作为电流倍增器连接到输出开关。还描述了串联等效偏置电路。

7. 发明授权

US07123177B2 System and method for stabilizing high order sigma delta modulators 失效
标题翻译：用于稳定高阶Σ-Δ调制器的系统和方法
公开(公告)号：US07123177B2
公开(公告)日：2006-10-17
申请号：US10640633
申请日：2003-08-14
申请人： Taiyi Cheng , Josephus van Engelen , Minsheng Wang
发明人： Taiyi Cheng , Josephus van Engelen , Minsheng Wang
IPC分类号： H03M3/00
CPC分类号： H03M3/444 , H03M3/43
摘要： A system and method is provided for stabilizing high order sigma delta modulators. The system includes an integrator having a limiter in the feedback path of the integrator. The integrator combines an input signal with a feedback signal generated by the limiter to produce an integrated output signal. The output signal is output to the next component of the sigma delta modulator. In addition, the output signal is fed back through the limiter. When an output signal received in the feedback path by the limiter exceeds the threshold value of the limiter, the limiter is activated and clamps the output signal to produce a limited signal. The limited signal is combined with the input signal to the integrator to produce the output signal.
摘要翻译：提供了一种用于稳定高阶Σ-Δ调制器的系统和方法。该系统包括在积分器的反馈路径中具有限幅器的积分器。积分器将输入信号与限幅器产生的反馈信号相结合，产生一个集成的输出信号。输出信号输出到Σ-Δ调制器的下一个分量。此外，输出信号通过限幅器反馈。当限制器在反馈路径中接收的输出信号超过限幅器的阈值时，限幅器被激活并钳位输出信号以产生有限的信号。有限信号与输入信号组合到积分器以产生输出信号。

8. 发明申请

US20050270203A1 Nonlinear mapping in digital-to-analog and analog-to-digital converters 有权
标题翻译：数模转换器和模数转换器的非线性映射
公开(公告)号：US20050270203A1
公开(公告)日：2005-12-08
申请号：US11124394
申请日：2005-05-09
申请人： Todd Brooks , Kevin Miller , Josephus Van Engelen
发明人： Todd Brooks , Kevin Miller , Josephus Van Engelen
IPC分类号： H03M3/00 , H03M7/36
CPC分类号： H03M7/3013
摘要： In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.
摘要翻译：在高保真数字调制器中，提供映射器以最小化多个数模转换器或模数转换器之间的量化噪声，抖动和串扰。映射器从量化器接收量化电平，并将量化电平映射到输出序列。映射器包括定义对应于每个量化级别的多个序列的表。每个序列包括具有多个值之一的两个或多个符号。映射器还包括选择多个序列之一作为输出序列的发生器。第一个输出序列的最后一个符号等于下一个输出序列的第一个符号，依此类推。发生器通过在接收到的每个量化级别的第一和第二序列之间交替来选择输出序列。发生器通过在接收到的每个奇数值量化电平具有正和负共模能量的序列之间交替来选择输出序列。

9. 发明授权

US08433020B2 High-speed serial data transceiver and related methods 有权
公开(公告)号：US08433020B2
公开(公告)日：2013-04-30
申请号：US11446144
申请日：2006-06-05
申请人： Aaron W. Buchwald , Michael Le , Josephus Van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron W. Buchwald , Michael Le , Josephus Van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H04L7/00
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

10. 发明申请

US20110184686A1 METHOD AND SYSTEM FOR COMPENSATING TEMPERATURE READINGS FROM A TEMPERATURE SENSING CRYSTAL INTEGRATED CIRCUIT 有权
标题翻译：从温度感测晶体集成电路补偿温度读数的方法和系统
公开(公告)号：US20110184686A1
公开(公告)日：2011-07-28
申请号：US13085407
申请日：2011-04-12
申请人： Todd Brooks , Vinay Chandrasekhar , Josephus Van Engelen , Jared Welz
发明人： Todd Brooks , Vinay Chandrasekhar , Josephus Van Engelen , Jared Welz
IPC分类号： G06F19/00 , G01K15/00
CPC分类号： G01R19/2506 , G01K7/32
摘要： Aspects of a method and system for compensating temperature readings from a temperature sensing crystal integrated circuit are provided. An electronic device may digitize a temperature indication received from a temperature sensing circuit, digitize one or more calibration voltages received from said temperature sensing circuit, and calculate a compensated temperature indication utilizing the digitized calibration voltage(s), and the digitized temperature indication, and data from a table that characterizes behavior of the temperature sensing circuit as a function of temperature. One or more circuits in the electronic device may be controlled based on the compensated temperature indication. The compensated temperature indication may compensate for a gain error and/or offset error of a digital to analog converter that digitizes the temperature indication and the calibration voltage(s). There may be two calibration voltages.
摘要翻译：提供了用于补偿来自温度感测晶体集成电路的温度读数的方法和系统的方面。电子设备可以数字化从温度检测电路接收的温度指示，数字化从所述温度检测电路接收的一个或多个校准电压，并且使用数字化校准电压和数字化温度指示来计算补偿温度指示，以及来自表格的数据表示温度感测电路的行为作为温度的函数。可以基于补偿的温度指示来控制电子设备中的一个或多个电路。补偿温度指示可以补偿数字化温度指示和校准电压的数模转换器的增益误差和/或偏移误差。可能有两个校准电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式