专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20200382092A1 METHODS OF MAKING ACOUSTIC WAVE DEVICES 审中-公开
公开(公告)号：US20200382092A1
公开(公告)日：2020-12-03
申请号：US16428860
申请日：2019-05-31
申请人： Dong Li , Ying Ma , Ge Yi , Zongrong Liu
发明人： Dong Li , Ying Ma , Ge Yi , Zongrong Liu
IPC分类号： H03H9/02 , H03H9/17
摘要： An acoustic wave device system with its piezoelectric layer originating from a single crystal piezoelectric wafer/substrate is invented along with sets of detailed process steps to fabricate such a device using wafer-to-wafer and/or die-to-wafer bonding technologies. The proposed device system is particularly good to make bulk acoustic wave (BAW) devices. Methods allowing the single crystal piezoelectric wafer/substrate to be re-used are also given. The proposed methods include detailed process steps to allow heterogeneous integration of electrical chips into the system in a very cost efficient manner. The invention provides a practical and low-cost approach to fabricate the radio frequency (RF) front end chip incorporating RF filters and electronic components integrated into a small footprint which is particularly useful for mobile device and RF stations.

2. 发明申请

US20210057242A1 Chip Front Surface Touchless Pick and Place Tool or Flip Chip Bonder 有权
公开(公告)号：US20210057242A1
公开(公告)日：2021-02-25
申请号：US16550109
申请日：2019-08-23
申请人： Yunjun Tang , Zongrong Liu , Ge Yi
发明人： Yunjun Tang , Zongrong Liu , Ge Yi
IPC分类号： H01L21/67 , H01L23/00 , H01L21/683
摘要： A piece of pick and place tool or a chip bonding equipment, which has innovative designs enabling chip(s) on a tape to get picked up without touching its front surface, is invented. The designs use levitation technologies to receive and hold the chips detached from the tape from a face-down position. A streamline design is also invented to provide better productivity. The invented pick and place tool or chip bonder is particularly useful for applications which require using chips with zero tolerance of particle and/or contamination on the chip front surfaces.

3. 发明申请

US20110147943A1 WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS 有权
标题翻译：可堆叠集成电路板的水平面钝化
公开(公告)号：US20110147943A1
公开(公告)日：2011-06-23
申请号：US13041192
申请日：2011-03-04
申请人： Simon J. S. McElrea , Terrence Caskey , Scott McGrath , DeAnn Eileen Melcher , Reynaldo Co , Lawrence Douglas Andrews, JR. , Weiping Pan , Grant Villavicencio , Yong Du , Scott Jay Crane , Zongrong Liu
发明人： Simon J. S. McElrea , Terrence Caskey , Scott McGrath , DeAnn Eileen Melcher , Reynaldo Co , Lawrence Douglas Andrews, JR. , Weiping Pan , Grant Villavicencio , Yong Du , Scott Jay Crane , Zongrong Liu
IPC分类号： H01L23/48 , H01L21/78
CPC分类号： H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3185 , H01L24/81 , H01L24/83 , H01L2221/68327 , H01L2221/6834 , H01L2221/68359 , H01L2221/68377 , H01L2224/2919 , H01L2224/81801 , H01L2224/83851 , H01L2924/14 , H01L2924/1461 , H01L2924/0665 , H01L2924/00014 , H01L2924/00
摘要： An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
摘要翻译：至少在晶片加工过程中至少施加电绝缘保形涂层至模具的活性（前）侧和一个或多个侧壁。此外，模具具有至少施加到活性（前）侧和侧壁的电绝缘保形涂层。此外，组件包括这种模具的叠层，电互连的模 - 芯; 并且组件包括这种管芯或这种管芯的堆叠，电连接到下面的电路（例如在基板或电路板中）。

4. 发明授权

US07923349B2 Wafer level surface passivation of stackable integrated circuit chips 有权
标题翻译：晶圆级表面钝化堆叠式集成电路芯片
公开(公告)号：US07923349B2
公开(公告)日：2011-04-12
申请号：US12142589
申请日：2008-06-19
申请人： Simon J. S. McElrea , Terrence Caskey , Scott McGrath , DeAnn Eileen Melcher , Reynaldo Co , Lawrence Douglas Andrews, Jr. , Weiping Pan , Grant Villavicencio , Yong Du , Scott Jay Crane , Zongrong Liu
发明人： Simon J. S. McElrea , Terrence Caskey , Scott McGrath , DeAnn Eileen Melcher , Reynaldo Co , Lawrence Douglas Andrews, Jr. , Weiping Pan , Grant Villavicencio , Yong Du , Scott Jay Crane , Zongrong Liu
IPC分类号： H01L21/46 , H01L21/78 , H01L21/301
CPC分类号： H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3185 , H01L24/81 , H01L24/83 , H01L2221/68327 , H01L2221/6834 , H01L2221/68359 , H01L2221/68377 , H01L2224/2919 , H01L2224/81801 , H01L2224/83851 , H01L2924/14 , H01L2924/1461 , H01L2924/0665 , H01L2924/00014 , H01L2924/00
摘要： An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
摘要翻译：至少在晶片加工过程中至少施加电绝缘保形涂层至模具的活性（前）侧和一个或多个侧壁。此外，模具具有至少施加到活性（前）侧和侧壁的电绝缘保形涂层。此外，组件包括这种模具的叠层，电互连的模 - 芯; 并且组件包括这种管芯或这种管芯的堆叠，电连接到下面的电路（例如在基板或电路板中）。

5. 发明授权

US08997832B1 Method of fabricating micrometer scale components 有权
标题翻译：制造微米级元件的方法
公开(公告)号：US08997832B1
公开(公告)日：2015-04-07
申请号：US12953311
申请日：2010-11-23
申请人： Zongrong Liu , Lei Wang
发明人： Zongrong Liu , Lei Wang
IPC分类号： B22D19/00 , B22D23/06
CPC分类号： G11B5/314 , B22D23/06 , B23K1/0006 , B23K31/02 , G11B5/4866 , G11B2005/0021
摘要： A method for manufacturing micrometer scale components comprises depositing a first metal on a substrate, depositing a second metal in a mold, and alloying the first and second metals together to form the component.
摘要翻译：一种用于制造微米尺度部件的方法包括在基底上沉积第一金属，在模具中沉积第二金属，并将第一和第二金属合金化以形成部件。

6. 发明申请

US20130307097A1 Magnetoresistive random access memory cell design 审中-公开
标题翻译：磁阻随机存取存储单元设计
公开(公告)号：US20130307097A1
公开(公告)日：2013-11-21
申请号：US13472085
申请日：2012-05-15
申请人： Ge Yi , Shaoping Li , Yunjun Tang , Zongrong Liu , Dujiang Wan
发明人： Ge Yi , Shaoping Li , Yunjun Tang , Zongrong Liu , Dujiang Wan
IPC分类号： H01L29/82
CPC分类号： H01L43/08
摘要： A magnetic memory cell comprises in-plane anisotropy tunneling magnetic junction (TMJ) and two fixed in-plane storage-stabilized layers, which splits on the both side of the data storage layer of the TMJ. The magnetizations of the said fixed in-plane storage-stabilized layers are all normal to that of the reference layer of TMJ but point to opposite direction. The existing of the storage-stabilized layers not only enhances the stability of the data storage, but also can reduce the critical current needed to flip the data storage layer via some specially added features.
摘要翻译：磁存储单元包括面内各向异性隧道磁结（TMJ）和两个固定的面内存储稳定层，其分散在TMJ的数据存储层的两侧。所述固定的面内储存稳定层的磁化与TMJ的参考层的磁化正好相反，但指向相反的方向。现有的存储稳定层不仅增强了数据存储的稳定性，而且还可以通过一些特别添加的功能来减少翻转数据存储层所需的临界电流。

7. 发明申请

US20130270661A1 Magnetoresistive random access memory cell design 审中-公开
标题翻译：磁阻随机存取存储单元设计
公开(公告)号：US20130270661A1
公开(公告)日：2013-10-17
申请号：US13448133
申请日：2012-04-16
申请人： Ge Yi , Shaoping Li , Yunjun Tang , Zongrong Liu
发明人： Ge Yi , Shaoping Li , Yunjun Tang , Zongrong Liu
IPC分类号： H01L29/82
CPC分类号： H01L43/08 , G11C11/161
摘要： A new magnetic memory cell comprises a perpendicular-anisotropy tunneling magnetic junction (TMJ) and a fixed in-plane spin-polarizing layer, which is separated from the perpendicular-anisotropy data storage layer of tunneling magnetic junction by a non-magnetic layer. The non-magnetic layer can be made of metallic or dielectric materials.
摘要翻译：新的磁存储单元包括垂直各向异性隧道磁结（TMJ）和固定的面内自旋偏振层，其通过非磁性层与隧道磁结的垂直各向异性数据存储层分离。非磁性层可以由金属或介电材料制成。

8. 发明申请

US20130252375A1 Magnet Assisted Alignment Method for Wafer Bonding and Wafer Level Chip Scale Packaging 审中-公开
标题翻译：用于晶圆接合和晶圆级芯片级封装的磁辅助对准方法
公开(公告)号：US20130252375A1
公开(公告)日：2013-09-26
申请号：US13429440
申请日：2012-03-26
申请人： Ge Yi , Zongrong Liu , Yunjun Tang , Shaoping Li
发明人： Ge Yi , Zongrong Liu , Yunjun Tang , Shaoping Li
IPC分类号： H01L23/00
CPC分类号： H01L24/83 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/80 , H01L24/81 , H01L24/94 , H01L24/97 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03612 , H01L2224/03614 , H01L2224/0362 , H01L2224/03826 , H01L2224/03827 , H01L2224/0401 , H01L2224/05009 , H01L2224/05073 , H01L2224/05082 , H01L2224/05083 , H01L2224/05084 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05547 , H01L2224/05576 , H01L2224/05578 , H01L2224/056 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/08146 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/1162 , H01L2224/13022 , H01L2224/13025 , H01L2224/131 , H01L2224/16146 , H01L2224/80121 , H01L2224/80143 , H01L2224/80169 , H01L2224/80801 , H01L2224/81121 , H01L2224/81143 , H01L2224/81169 , H01L2224/81801 , H01L2224/94 , H01L2224/97 , H01L2924/01322 , H01L2924/1461 , H01L2924/00015 , H01L2924/00014 , H01L2924/014 , H01L2924/01026 , H01L2924/01028 , H01L2924/01078 , H01L2924/01024 , H01L2224/80 , H01L2224/81 , H01L2224/03 , H01L2224/11 , H01L2924/00
摘要： A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.
摘要翻译：提出了一种高精度的高通量对准方法，可用于晶圆到晶圆，晶片到晶圆或芯片间的接合。该方案实现了使用晶片级处理在两个部件（晶片或芯片）上预先设计和制造的配对图案化磁体。在接合开始之前，图案化磁体中的磁化可以被设定为预定的配置。当两个部件在粗对准之后被购买成靠近时，磁力将使磁体对在一起，并将其上的图案化磁体与其另一部件上的镜像或互补的图案化磁体对准，以最小化整个磁能的配对磁铁。提出了一些具有独特优点的图案化磁体结构和材料作为用于自对准目的的磁体对的示例。该方法能够在磁力下通过图案化的磁体在接合界面处实现牢固的接触，从而避免由于液相的形成引起的晶片牵伸。

9. 发明授权

US08518748B1 Method and system for providing a laser submount for an energy assisted magnetic recording head 有权
标题翻译：提供用于能量辅助磁记录头的激光基座的方法和系统
公开(公告)号：US08518748B1
公开(公告)日：2013-08-27
申请号：US13172583
申请日：2011-06-29
申请人： Lei Wang , Zongrong Liu , Pezhman Monadgemi
发明人： Lei Wang , Zongrong Liu , Pezhman Monadgemi
IPC分类号： H01L21/00
CPC分类号： H01L23/49811 , B23K26/364 , B23K26/40 , B23K2103/50 , G11B5/314 , G11B7/12 , G11B2005/0021 , H01L2924/0002 , H01L2924/00
摘要： A method and system for providing a laser diode submount for use in an energy assisted magnetic recording disk drive are described. A portion of a silicon substrate is removed, forming trenches therein. Each trench has sidewalls, surrounds a silicon island corresponding to a laser diode submount, and corresponds to a thickness of the laser diode submount. The silicon island has a top surface and a facets corresponding to the trench sidewalls. Insulator(s) for the top surface and facets of the silicon island are provided. Metallization is provided on the top surface and facets of the silicon island. A first portion of the metallization on the top surface corresponds to under bump metal (UBM) for solder pad(s). A second portion of the metallization corresponds to electrical traces. Solder pad(s) are provided on the UBM. The silicon island is released from the silicon substrate.
摘要翻译：描述了一种用于提供用于能量辅助磁记录盘驱动器中的激光二极管基座的方法和系统。去除一部分硅衬底，在其中形成沟槽。每个沟槽具有侧壁，围绕对应于激光二极管基座的硅岛，并且对应于激光二极管基座的厚度。硅岛具有顶表面和对应于沟槽侧壁的面。提供了用于硅岛顶表面和小平面的绝缘体。在硅岛的顶表面和小平面上提供金属化。顶表面上的金属化的第一部分对应于用于焊盘的下凸块金属（UBM）。金属化的第二部分对应于电迹线。焊盘在UBM上提供。硅岛从硅衬底释放出来。

10. 发明申请

US20130114334A1 Magnetoresistive random access memory cell with independently operating read and write components 审中-公开
标题翻译：具有独立操作的读写组件的磁阻随机存取存储单元
公开(公告)号：US20130114334A1
公开(公告)日：2013-05-09
申请号：US13288860
申请日：2011-11-03
申请人： Ge Yi , Shaoping Li , Dong Li , Yunjun Tang , Zongrong Liu
发明人： Ge Yi , Shaoping Li , Dong Li , Yunjun Tang , Zongrong Liu
IPC分类号： G11C11/15
CPC分类号： H01L43/08 , G11C11/16 , G11C11/161 , G11C11/1675
摘要： A new class of the memory cell is proposed. There are two separated pulse data writing and sensing current paths. The in-plane pulse current is used to flip the magnetization direction of the perpendicular-anisotropy data storage layer sandwiched between a heavy metal writing current-carrying layer and a dielectric layer. The magnetization state within data storage layer is detected by the patterned perpendicular-anisotropy tunneling magnetoresistive (TMR) stack via the output potential of the stack. Two detailed memory cells are proposed: in one proposed cell, the data storage layer is independent from but kept close to the sensing TMR stack, whose magnetization orientation affects magnetization configuration within the free layer of the TMR stack, therefor ultimately affects the output potential of the stack; in the other proposed cell, the perpendicular-anisotropy data storage layer is the free layer of the sensing TMR stack, whose magnetization state will directly affect the output potential of the stack when sensing current passes through.
摘要翻译：提出了一类新的存储单元。有两个分离的脉冲数据写入和感测电流路径。面内脉冲电流用于翻转夹在重金属写入载流层和电介质层之间的垂直各向异性数据存储层的磁化方向。数据存储层内的磁化状态通过图案化的垂直各向异性隧道磁阻（TMR）堆叠通过堆叠的输出电位来检测。提出了两个详细的存储单元：在一个提出的单元中，数据存储层独立于但保持靠近感测TMR堆栈，其磁化方向影响TMR堆栈自由层内的磁化配置，从而最终影响堆栈在另一个提出的单元中，垂直各向异性数据存储层是感测TMR堆栈的自由层，当感测电流通过时，其磁化状态将直接影响堆叠的输出电位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式