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1. 发明授权

US5780870A Semiconductor device and a process of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5780870A
公开(公告)日：1998-07-14
申请号：US723366
申请日：1996-09-30
申请人： Hitoshi Maeda , Yukinori Hirose , Yuichi Yokoyama
发明人： Hitoshi Maeda , Yukinori Hirose , Yuichi Yokoyama
IPC分类号： H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/66 , H01L21/768 , H01L23/544 , H01L23/48 , H01L29/04
CPC分类号： H01L22/20 , H01L22/34
摘要： A semiconductor device is provided for convenient checking of etching states of semiconductor layers, along with a process for its preparation, wherein a test layer is formed on the same wafer where a semiconductor product is manufactured, and concurrently with and under the same formation conditions as formation a target layer forming a part of the semiconductor product, wherein the test layer is formed on a first layer and on a second layer interposed between a portion of the test layer and the first layer, with one of the first and second layers having the same etching properties as the target layer and the other of the first and second layers having different etching characteristics from the target layer. After etching the test layer and target layer concurrently to form holes in each the amount of the etching of the holes can be measured by an electron microscope, and the amount of etching in the target layer of the semiconductor product is controlled from the state of the etching reaching to the lower layer, either the first or second layer, below the test layer.
摘要翻译：提供一种半导体器件，用于方便地检查半导体层的蚀刻状态，以及其制备方法，其中测试层形成在制造半导体产品的同一晶片上，并且与相同的形成条件形成形成所述半导体产品的一部分的目标层，其中所述测试层形成在第一层上，并且在插入在所述测试层的一部分与所述第一层之间的第二层上，所述第一层和所述第二层中的一个具有与目标层相同的蚀刻性能和与目标层具有不同蚀刻特性的第一和第二层中的另一个相同。在通过电子显微镜测量每个蚀刻孔数的同时蚀刻测试层和目标层之后形成孔，并且半导体产品的目标层中的蚀刻量由蚀刻到达测试层下方的第一层或第二层的下层。

2. 发明授权

US08946895B2 Semiconductor device, manufacturing method of semiconductor device, semiconductor manufacturing and inspecting apparatus, and inspecting apparatus 有权
标题翻译：半导体装置，半导体装置的制造方法，半导体制造和检查装置以及检查装置
公开(公告)号：US08946895B2
公开(公告)日：2015-02-03
申请号：US12389479
申请日：2009-02-20
申请人： Takahiko Kato , Hiroshi Nakano , Haruo Akahoshi , Yuuji Takada , Yoshimi Sudo , Tetsuo Fujiwara , Itaru Kanno , Tomoryo Shono , Yukinori Hirose
发明人： Takahiko Kato , Hiroshi Nakano , Haruo Akahoshi , Yuuji Takada , Yoshimi Sudo , Tetsuo Fujiwara , Itaru Kanno , Tomoryo Shono , Yukinori Hirose
IPC分类号： H01L23/48 , H01L23/532 , H01L21/768
CPC分类号： H01L22/12 , H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L21/76879 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.
摘要翻译：具有包括可以减小表面空隙的碱性晶体结构的Cu布线的半导体器件和用于半导体器件的检查技术。在半导体装置中，通过指定阻挡层和种子层，并设定具有一致位点网格（CSL）边界的占有比例（频率），表面空隙可以降低到当前实用水平的1/10以下，具有对于Cu布线的所有晶界，晶界Sigma值为27以下，为60％以上。或者，可以通过指定阻挡层和种子层并且将具有晶界Sigma值3的重合位点晶格（CSL）边界的占有比例（频率）设置为全部晶粒，可以获得类似的表面空隙降低效果 Cu布线的边界为40％以上。

3. 发明申请

US20090218694A1 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR MANUFACTURING AND INSPECTING APPARATUS, AND INSPECTING APPARATUS 有权
标题翻译：半导体器件，半导体器件的制造方法，半导体制造和检查装置以及检查装置
公开(公告)号：US20090218694A1
公开(公告)日：2009-09-03
申请号：US12389479
申请日：2009-02-20
申请人： Takahiko KATO , Hiroshi NAKANO , Haruo AKAHOSHI , Yuuji TAKADA , Yoshimi SUDO , Tetsuo FUJIWARA , Itaru KANNO , Tomoryo SHONO , Yukinori HIROSE
发明人： Takahiko KATO , Hiroshi NAKANO , Haruo AKAHOSHI , Yuuji TAKADA , Yoshimi SUDO , Tetsuo FUJIWARA , Itaru KANNO , Tomoryo SHONO , Yukinori HIROSE
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L22/12 , H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L21/76879 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.
摘要翻译：具有包括可以减小表面空隙的碱性晶体结构的Cu布线的半导体器件和用于半导体器件的检查技术。在半导体装置中，通过指定阻挡层和种子层，并设定具有一致位点网格（CSL）边界的占有比例（频率），表面空隙可以降低到当前实用水平的1/10以下，具有对于Cu布线的所有晶界，晶界Sigma值为27以下，为60％以上。或者，可以通过指定阻挡层和种子层并且将具有晶界Sigma值3的重合位点晶格（CSL）边界的占有比例（频率）设置为全部晶粒，可以获得类似的表面空隙降低效果 Cu布线的边界为40％以上。

4. 发明授权

US06452174B1 Charged particle beam apparatus and method of controlling same 失效
标题翻译：带电粒子束装置及其控制方法
公开(公告)号：US06452174B1
公开(公告)日：2002-09-17
申请号：US09559075
申请日：2000-04-27
申请人： Yukinori Hirose , Kazuhito Honda
发明人： Yukinori Hirose , Kazuhito Honda
IPC分类号： H01J37244
CPC分类号： H01J37/3056 , H01J37/304
摘要： An FIB apparatus (101) includes a probe (2) grounded through an ammeter (12). An FIB (1B) is directed to impinge upon a sample (5) while a driver (22) is controlled to gradually decrease a distance between the probe (2) and the sample (5). With the probe (2) in non-contacting relationship with the sample (5), current generated in the sample (5) by the FIB (1B) impingement flows inwardly of the sample (5). With the probe (2) in contacting relationship with the sample (5), on the other hand, the current generated in the sample (5) flows toward the probe (2). Thus, current flowing through the probe (2) increases when contact is made between the probe (2) and the sample (5). The contact between the probe (2) and the sample (5) is detected based on the amount of change in the current flowing through the probe (2) which is monitored by the ammeter (12). The FIB apparatus can reliably detect the contact between the probe and the sample without the need to provide an additional power supply for detection of the contact therebetween.
摘要翻译： FIB装置（101）包括通过电流表（12）接地的探针（2）。在控制驱动器（22）以逐渐减小探针（2）和样品（5）之间的距离的情况下，FIB（1B）被引向冲击样品（5）。探针（2）与样品（5）处于非接触关系时，通过FIB（1B）冲击在样品（5）中产生的电流在样品（5）内部流动。另一方面，在探针（2）与样品（5）接触的情况下，样品（5）中产生的电流朝向探针（2）流动。因此，当在探针（2）和样品（5）之间进行接触时，流过探针（2）的电流增加。基于由电流表（12）监视的探针（2）流过的电流的变化量来检测探针（2）和样品（5）之间的接触。 FIB装置可以可靠地检测探针和样品之间的接触，而不需要提供用于检测其间的接触的附加电源。

5. 发明授权

US06826971B2 Fabrication method for sample to be analyzed 失效
标题翻译：待分析样品的制备方法
公开(公告)号：US06826971B2
公开(公告)日：2004-12-07
申请号：US10176658
申请日：2002-06-24
申请人： Yukinori Hirose
发明人： Yukinori Hirose
IPC分类号： G01N100
CPC分类号： G01N1/28 , H01J2237/2511
摘要： The semiconductor substrate is removed from a wafer or a chip wherein a defect has occurred and, thereby, the surface, which faces the substrate, that contacts the semiconductor substrate in an element formation portion is exposed. A cross section of the element formation portion is exposed through the irradiation of a focused ion beam. Furthermore, a microprober is adhered to the sample and, then, the sample including a foreign substance that is considered to be a cause of defects is detached from the element formation portion. The extracted sample is moved onto a supporting base for analysis and the sample is secured to the supporting base for analysis by forming a tungsten film. Thereby, detailed information can be gained concerning a defective portion that is located, in particular, in the vicinity of the surface of the semiconductor substrate from among defective portions that have occurred in the semiconductor device.
摘要翻译：从发生缺陷的晶片或芯片去除半导体衬底，从而露出与元件形成部分中的与半导体衬底接触的面向衬底的表面。元件形成部分的横截面通过照射聚焦离子束而暴露。此外，将微孔粘附到样品上，然后将包含被认为是缺陷原因的异物的样品从元件形成部分分离。将提取的样品移动到支撑基底上进行分析，并通过形成钨膜将样品固定到支撑基底进行分析。由此，可以从在半导体器件中发生的缺陷部分中的特别是位于半导体衬底的表面附近的缺陷部分获得详细的信息。

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