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1. 发明授权

US08181064B2 Information processing apparatus for inhibiting instructions, saving and restoring internal information in response to abnormality in redundant processor system 失效
标题翻译：用于抑制指令的信息处理装置，响应于冗余处理器系统的异常而保存和恢复内部信息
公开(公告)号：US08181064B2
公开(公告)日：2012-05-15
申请号：US12659896
申请日：2010-03-24
申请人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
发明人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
IPC分类号： G06F11/00
CPC分类号： G06F11/1658 , G06F11/165 , G06F11/1679 , G06F2201/81
摘要： A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in a firmware hub instructs the northbridge to inhibit an external instruction. In addition, the firmware saves the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU saved on the memory to all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.
摘要翻译：当检测到冗余CPU的同步中断时，北桥停止发生错误的异常CPU总线的操作，并且固件集线器中的固件指示北桥禁止外部指令。此外，固件还可以将连接到普通CPU总线的普通CPU的内部信息和高速缓存数据保存在存储器上，并且北桥将重置到家庭系统板中的所有CPU。然后，固件将保存在存储器上的CPU的内部信息恢复到所有CPU，并指示北桥取消对外部指令的禁止。

2. 发明授权

US08090912B2 Multiprocessor system, system board, and cache replacement request handling method 有权
标题翻译：多处理器系统，系统板和缓存替换请求处理方法
公开(公告)号：US08090912B2
公开(公告)日：2012-01-03
申请号：US11790265
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0833
摘要： A request issued by the CPU is output from the local arbiter by way of the CPU bus and the CPU-issued request queue. The cache replacement request loop-back circuit determines at the loop-back determination circuit whether the outputted request is a cache replacement request or not. A request other than a cache replacement request is output onto the local bus. A cache replacement request is output to the selector and sent to the request handling section when there is no valid request on the global bus.
摘要翻译：通过CPU总线和CPU发出的请求队列，从本地仲裁器输出CPU发出的请求。高速缓存替换请求环回电路在环回确定电路中确定输出的请求是否是高速缓存替换请求。除了缓存替换请求之外的请求被输出到本地总线上。当全局总线上没有有效请求时，高速缓存替换请求被输出到选择器并发送到请求处理部分。

3. 发明授权

US07805576B2 Information processing system, information processing board, and method of updating cache tag and snoop tag 有权
标题翻译：信息处理系统，信息处理板，缓存标签和窥探标签更新方法
公开(公告)号：US07805576B2
公开(公告)日：2010-09-28
申请号：US11740984
申请日：2007-04-27
申请人： Yuka Hosokawa , Takaharu Ishizuka , Makoto Hataida , Toshikazu Ueki
发明人： Yuka Hosokawa , Takaharu Ishizuka , Makoto Hataida , Toshikazu Ueki
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0831
摘要： In an information processing system loaded with a CPU having cache and a system controller having a copy of a tag of the cache (snoop tag), and the CPU not issuing replacement information about the cache tag, the number of WAYs of the snoop tags in the system controller is larger than the number of WAYs of the cache tags in the CPU to reduce a cache miss rate and suppress the degradation of performance by suppressing excess replacement of the cache tags in the CPU.
摘要翻译：在装载有具有高速缓存的CPU的信息处理系统和具有高速缓存（snoop标签）的标签的副本的系统控制器以及不发出关于高速缓存标签的替换信息的CPU的情况下，系统控制器大于CPU中缓存标签的方式数量，以减少高速缓存未命中率，并通过抑制CPU中高速缓存标签的过多替换来抑制性能下降。

4. 发明授权

US07779209B2 System controller, snoop tag modification method and information processing apparatus having snoop tag modification function 有权
标题翻译：系统控制器，snoop标签修改方法和具有snoop标签修改功能的信息处理设备
公开(公告)号：US07779209B2
公开(公告)日：2010-08-17
申请号：US11790263
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0822 , G06F12/0831
摘要： In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the address is registered in S (Shared state) in only any one of the snoop tags corresponding to the CPUs in which the same address is registered.
摘要翻译：在多处理器系统中，系统控制器包括窥探标签，这些标签是由各个CPU保留的缓存标签上的复制信息。如果在连接到同一CPU总线的每个CPU的缓存标签中的S（共享状态）中登记相同的地址，则只在与CPU对应的任何一个snoop标签中的S（共享状态）中注册该地址其中注册了相同的地址。

5. 发明授权

US07467261B2 Dual storage apparatus and control method for the dual storage apparatus 有权
标题翻译：双存储设备的双存储设备和控制方法
公开(公告)号：US07467261B2
公开(公告)日：2008-12-16
申请号：US11237934
申请日：2005-09-29
申请人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
发明人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
IPC分类号： G06F12/00
CPC分类号： G06F11/1008 , G06F11/1666 , G06F11/20 , G11C5/005
摘要： A dual storage apparatus is provided that comprises a first and a second memories for respectively retaining a set of identical data and a selector for selecting either of the two (2) sets of the data respectively read from the first and the second memory based on a read control signal inputted into the selector, having a request management unit for, when the read control signal has been inputted, attaching an identifier for identifying the read control signal to the inputted read control signal and outputting the signal and the identifier; and a plurality of memory control units for each of the first and the second memories. The dual storage apparatus detects a synchronization error by verifying coincidence of the identifier attached by the request management unit and controls the selector such that the data from a system from which no synchronization error has been detected.
摘要翻译：提供了一种双存储装置，其包括用于分别保存一组相同数据的第一和第二存储器，以及用于选择从第一和第二存储器分别读取的两（2）组数据中的任何一个基于读取控制信号输入到选择器中，具有请求管理单元，当输入了读取控制信号时，将用于识别读取控制信号的标识符附加到所输入的读取控制信号并输出该信号和标识符; 以及用于第一和第二存储器中的每一个的多个存储器控制单元。双存储装置通过验证由请求管理单元附加的标识符的一致性来检测同步错误，并且控制选择器使得来自未检测到同步错误的系统的数据。

6. 发明申请

US20080046792A1 Node device, control device, control method and control program 有权
标题翻译：节点装置，控制装置，控制方法和控制程序
公开(公告)号：US20080046792A1
公开(公告)日：2008-02-21
申请号：US11785759
申请日：2007-04-19
申请人： Takashi Yamamoto , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takashi Yamamoto , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： H04L1/00
CPC分类号： H04L1/004 , H04L1/0082 , H04L2001/0097
摘要： A control device managing a plurality of nodes transmitting and receiving data containing an error correcting code, comprises means accepting, when any one of the nodes detects an uncorrectable error from the data containing the error correcting code, a signal transmitted by the node detecting the error, means judging from a record of the detection of a first node, when accepting the signal from a second node receiving data transmitted by the first node, whether or not the first node has detected the uncorrectable error from the data transmitted to the second node, and means stopping, when the first node has detected the uncorrectable error from the data transmitted to the second node, a process attributed to the acceptance of the signal from the second node.
摘要翻译：管理发送和接收包含纠错码的数据的多个节点的控制装置包括当任何一个节点从包含纠错码的数据中检测到不可校正的错误时，接收由检测到错误的节点发送的信号从第一节点接收到的数据接收来自第二节点的信号，从第一节点的检测记录中判断第一节点是否从发送到第二节点的数据检测到不可校正的错误，并且意味着当第一节点从发送到第二节点的数据中检测到不可校正的错误时，停止归因于来自第二节点的信号的接受的处理。

7. 发明申请

US20080046664A1 Control device for snoop tag 失效
标题翻译：窥探标签控制装置
公开(公告)号：US20080046664A1
公开(公告)日：2008-02-21
申请号：US11790272
申请日：2007-04-24
申请人： Makoto Hataida , Toshikazu Ueki , Takaharu Ishizuka , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Makoto Hataida , Toshikazu Ueki , Takaharu Ishizuka , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/123
摘要： To prevent a decrease in performance of controlling a snoop tag. A queue is stored with REPLACE target WAY information and an index as an entry associated with a REPLACE request received from a processor, the index stored in the queue is compared with an index of a subsequent READ request, and, as a result of the comparison, a process based on the index-coincident READ request is executed with respect to the snoop tag corresponding to a content of a cache memory of the processor. Further, the REPLACE target WAY information of the READ request is replaced with the WAY information in the index-coincident entry within the queue.
摘要翻译：以防止控制snoop标签的性能下降。存储REPLACE目标WAY信息和索引作为与从处理器接收到的REPLACE请求相关联的条目的队列，将存储在队列中的索引与后续READ请求的索引进行比较，并且作为比较的结果相对于与处理器的高速缓冲存储器的内容相对应的窥探标签，执行基于索引一致的READ请求的处理。此外，READ请求的REPLACE目标WAY信息被队列中符合条件的条目中的WAY信息所替代。

8. 发明申请

US20110320901A1 DATA TRANSFER DEVICE AND CONTROL METHOD OF DATA TRANSFER DEVICE 有权
标题翻译：数据传输设备和数据传输设备的控制方法
公开(公告)号：US20110320901A1
公开(公告)日：2011-12-29
申请号：US13227852
申请日：2011-09-08
申请人： Kenta SATO , Takashi Yamamoto , Toshikazu Ueki , Yuka Hosokawa
发明人： Kenta SATO , Takashi Yamamoto , Toshikazu Ueki , Yuka Hosokawa
IPC分类号： H04L1/08 , G06F11/14
CPC分类号： H04L1/00 , H03M13/09 , H04L1/0061 , H04L1/1829 , H04L1/1835 , H04L1/242
摘要： A data transfer device includes a data transmitting circuit includes an error detection code generating unit generating an error detection code for detecting an error in the data, and a transmission unit transmitting the data and the error detection code together with retransmit enable information representing that corresponding data transmitted before the former data or transmitted next can be retransmitted, the data receiving circuit includes a reception unit receiving the transmitted data, the transmitted error detection code and the transmitted retransmit enable information, an error detection unit detecting the error in the received data based on the error detection code, an error data retaining unit retaining the data in which an error is detected when the reception unit receives the retransmit enable information, and an error data comparing unit that comparing the error detected data retained in the error data retaining unit with corresponding data that is retransmitted.
摘要翻译：数据传送装置包括数据发送电路，包括产生用于检测数据中的错误的错误检测码的错误检测码生成单元，以及发送数据和错误检测码的发送单元以及表示相应数据的再发送使能信息数据接收电路包括接收发送数据的接收单元，所发送的错误检测码和所发送的重传使能信息，错误检测单元，基于接收到的数据，基于误差检测码，当接收单元接收到重传使能信息时保持检测到错误的数据的误差数据保持单元;以及误差数据比较单元，其将保留在误差数据保持单元中的错误检测数据与相应的重发数据

9. 发明申请

US20100228507A1 TRACE DEVICE AND TRACE METHOD FOR FAILURE ANALYSIS 审中-公开
标题翻译：用于故障分析的跟踪设备和跟踪方法
公开(公告)号：US20100228507A1
公开(公告)日：2010-09-09
申请号：US12714939
申请日：2010-03-01
申请人： Yuka HOSOKAWA , Takashi Yamamoto , Toshikazu Ueki , Kenta Sato
发明人： Yuka HOSOKAWA , Takashi Yamamoto , Toshikazu Ueki , Kenta Sato
IPC分类号： G06F19/00 , G01R31/00
CPC分类号： G01R31/31705
摘要： A trace device for tracing data in an LSI includes a trace data storing unit that stores trace data, a trace target determination unit that determines whether to store trace data of one of a plurality of trace targets in the trace data storing unit based on an operating state of a system including the LSI and based on a failure occurrence report reported from any of the trace targets in response to an occurrence of an error in the trace target residing in the LSI and a trace target selection unit that selects the trace data to be stored in the trace data storing unit out of the trace data from the plurality of trace targets based on the determining by the trace target determination unit, and stores the selected trace data in the trace data storing unit.
摘要翻译：用于在LSI中跟踪数据的跟踪装置包括存储跟踪数据的跟踪数据存储单元，跟踪目标确定单元，其基于操作确定是否将多个跟踪目标中的一个跟踪数据存储在跟踪数据存储单元中包括LSI的系统的状态，并且基于从任何跟踪目标报告的响应于驻留在LSI中的跟踪目标中的错误的发生的故障发生报告和选择跟踪数据的跟踪目标选择单元基于轨迹目标确定单元的确定，从多个跟踪目标中的跟踪数据中存储在跟踪数据存储单元中，并将所选择的跟踪数据存储在跟踪数据存储单元中。

10. 发明申请

US20100191942A1 Information processor and control method 失效
标题翻译：信息处理器和控制方法
公开(公告)号：US20100191942A1
公开(公告)日：2010-07-29
申请号：US12659896
申请日：2010-03-24
申请人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
发明人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
IPC分类号： G06F9/30
CPC分类号： G06F11/1658 , G06F11/165 , G06F11/1679 , G06F2201/81
摘要： A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU save on the memory to the all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.
摘要翻译：北桥在检测到冗余CPU的同步中断时，停止发生错误的异常CPU总线的运行，FWH中的固件指示北桥禁止外部指令。此外，固件还保存连接到普通CPU总线的正常CPU的内部信息，并将存储器上的数据缓存，并将北桥问题重置到家庭系统板中的所有CPU。然后，固件将CPU的内部信息恢复到所有CPU的存储器上，并指示北桥取消对外部指令的禁止。

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