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1. 发明授权

US08499125B2 Control device for snoop tag 失效
标题翻译：窥探标签控制装置
公开(公告)号：US08499125B2
公开(公告)日：2013-07-30
申请号：US11790272
申请日：2007-04-24
申请人： Makoto Hataida , Toshikazu Ueki , Takaharu Ishizuka , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Makoto Hataida , Toshikazu Ueki , Takaharu Ishizuka , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0822 , G06F12/123
摘要： To prevent a decrease in performance of controlling a snoop tag. A queue is stored with REPLACE target WAY information and an index as an entry associated with a REPLACE request received from a processor, the index stored in the queue is compared with an index of a subsequent READ request, and, as a result of the comparison, a process based on the index-coincident READ request is executed with respect to the snoop tag corresponding to a content of a cache memory of the processor. Further, the REPLACE target WAY information of the READ request is replaced with the WAY information in the index-coincident entry within the queue.
摘要翻译：以防止控制snoop标签的性能下降。存储REPLACE目标WAY信息和索引作为与从处理器接收到的REPLACE请求相关联的条目的队列，将存储在队列中的索引与后续READ请求的索引进行比较，并且作为比较的结果相对于与处理器的高速缓冲存储器的内容相对应的窥探标签，执行基于索引一致的READ请求的处理。此外，READ请求的REPLACE目标WAY信息被队列中符合条件的条目中的WAY信息所替代。

2. 发明申请

US20100191942A1 Information processor and control method 失效
标题翻译：信息处理器和控制方法
公开(公告)号：US20100191942A1
公开(公告)日：2010-07-29
申请号：US12659896
申请日：2010-03-24
申请人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
发明人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
IPC分类号： G06F9/30
CPC分类号： G06F11/1658 , G06F11/165 , G06F11/1679 , G06F2201/81
摘要： A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU save on the memory to the all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.
摘要翻译：北桥在检测到冗余CPU的同步中断时，停止发生错误的异常CPU总线的运行，FWH中的固件指示北桥禁止外部指令。此外，固件还保存连接到普通CPU总线的正常CPU的内部信息，并将存储器上的数据缓存，并将北桥问题重置到家庭系统板中的所有CPU。然后，固件将CPU的内部信息恢复到所有CPU的存储器上，并指示北桥取消对外部指令的禁止。

3. 发明申请

US20080046695A1 System controller, identical-address-request-queuing preventing method, and information processing apparatus having identical-address-request-queuing preventing function 有权
标题翻译：系统控制器，相同地址请求排队防止方法和具有相同地址请求排队防止功能的信息处理装置
公开(公告)号：US20080046695A1
公开(公告)日：2008-02-21
申请号：US11790266
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F9/30 , G06F12/00
CPC分类号： G06F13/1642
摘要： In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of an issued request for cache replace request matches an address of a request retained by the CPU-issued request queue, the issued request for the cache replace request is not retried but is queued in the CPU-issued request queue when the address of the issued request for the cache replace request does not match the entire address retained by the input-request retaining section.
摘要翻译：在包括CPU发出的请求队列的系统控制器中，具有处理具有相同地址的多个请求的电路不被输入到CPU发出的请求队列，除了高速缓存替换请求以外的最新请求被保留部分。因此，即使发出的请求高速缓存替换请求的地址与CPU发出的请求队列所保留的请求的地址相匹配，也不会重新发出对高速缓存替换请求的发出请求，而是在CPU发出的请求队列中排队当发出的缓存替换请求的地址与输入请求保留部分保留的整个地址不匹配时。

4. 发明申请

US20080046663A1 System controller, snoop tag modification method and information processing apparatus having snoop tag modificaton function 有权
标题翻译：系统控制器，snoop标签修改方法和具有snoop标签修改功能的信息处理设备
公开(公告)号：US20080046663A1
公开(公告)日：2008-02-21
申请号：US11790263
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0831
摘要： In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the address is registered in S (Shared state) in only any one of the snoop tags corresponding to the CPUs in which the same address is registered.
摘要翻译：在多处理器系统中，系统控制器包括窥探标签，这些标签是由各个CPU保留的缓存标签上的复制信息。如果在连接到同一CPU总线的每个CPU的缓存标签中的S（共享状态）中登记相同的地址，则只在与CPU对应的任何一个snoop标签中的S（共享状态）中注册该地址其中注册了相同的地址。

5. 发明申请

US20060212656A1 Dual storage apparatus and control method for the dual storage apparatus 有权
标题翻译：双存储设备的双存储设备和控制方法
公开(公告)号：US20060212656A1
公开(公告)日：2006-09-21
申请号：US11237934
申请日：2005-09-29
申请人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
发明人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
IPC分类号： G06F12/00
CPC分类号： G06F11/1008 , G06F11/1666 , G06F11/20 , G11C5/005
摘要： A dual storage apparatus is provided that comprises a first and a second memories for respectively retaining a set of identical data and a selector for selecting either of the two (2) sets of the data respectively read from the first and the second memory based on a read control signal inputted into the selector, having a request management unit for, when the read control signal has been inputted, attaching an identifier for identifying the read control signal to the inputted read control signal and outputting the signal and the identifier; and a plurality of memory control units for each of the first and the second memories. The dual storage apparatus detects a synchronization error by verifying coincidence of the identifier attached by the request management unit and controls the selector such that the data from a system from which no synchronization error has been detected.
摘要翻译：提供了一种双存储装置，其包括用于分别保存一组相同数据的第一和第二存储器，以及用于选择从第一和第二存储器分别读取的两（2）组数据中的任何一个基于读取控制信号输入到选择器中，具有请求管理单元，当输入了读取控制信号时，将用于识别读取控制信号的标识符附加到所输入的读取控制信号并输出该信号和标识符; 以及用于第一和第二存储器中的每一个的多个存储器控制单元。双存储装置通过验证由请求管理单元附加的标识符的一致性来检测同步错误，并且控制选择器使得来自未检测到同步错误的系统的数据。

6. 发明授权

US08078920B2 Information processing device and error processing method 失效
标题翻译：信息处理装置和误差处理方法
公开(公告)号：US08078920B2
公开(公告)日：2011-12-13
申请号：US12554318
申请日：2009-09-04
申请人： Atsushi Morosawa , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Takashi Yamamoto , Daisuke Itou
发明人： Atsushi Morosawa , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Takashi Yamamoto , Daisuke Itou
IPC分类号： G06F11/00
CPC分类号： G06F11/1658 , G06F11/1641 , G06F11/165 , G06F11/1687
摘要： An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.
摘要翻译：具有能够彼此同步操作的两个处理单元的信息处理装置包括：能够向两个处理单元输出相同信号的公共单元; 分别提供给处理单元的检测单元，并分别检测相应处理单元中发生的错误; 比较来自两个处理单元的输出的比较单元; 以及控制单元，其基于检测单元的检测结果和比较单元的比较结果来控制从处理单元到公共单元的信号，并且如果检测单元同时检测到相同类型的错误，则确定，错误是由于公共单元的错误。

7. 发明授权

US07694106B2 Multiprocessor system 有权
标题翻译：多处理器系统
公开(公告)号：US07694106B2
公开(公告)日：2010-04-06
申请号：US11785891
申请日：2007-04-20
申请人： Toshikazu Ueki , Takaharu Ishizuka , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Toshikazu Ueki , Takaharu Ishizuka , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F9/00
CPC分类号： G06F12/0813 , G06F12/1072
摘要： A multiprocessor system includes a judging unit judging whether a read command inputted to a global address crossbar is a read command to a memory on an own system board, an executing unit speculatively executing, when the judging unit judges that the read command is a read command to the memory on the own system board, the read command before global access based on an address notified from the global address crossbar, a setting unit setting for queuing data read from the memory in a data queue provided on a CPU without queuing the data in a data queue provided on the memory, and an instructing unit instructing, based on notification from the global address crossbar, the data queue provided on the CPU to discard the data or transmit the data to the CPU.
摘要翻译：多处理器系统包括判断单元，判断单元判断输入到全局地址交叉开关的读取命令是否是对自身系统板上的存储器的读取命令，当判断单元判断读取命令是读取命令时，执行单元推测执行基于从全局地址交叉开关通知的地址，在全局访问之前的读取命令，在CPU上提供的数据队列中从存储器读取数据的设置单元设置，而不排队数据设置在存储器上的数据队列，以及指示单元，根据来自全局地址交叉开关的通知指示CPU上提供的数据队列，丢弃数据或将数据发送到CPU。

8. 发明申请

US20080046694A1 Multiprocessor system 有权
标题翻译：多处理器系统
公开(公告)号：US20080046694A1
公开(公告)日：2008-02-21
申请号：US11785891
申请日：2007-04-20
申请人： Toshikazu Ueki , Takaharu Ishizuka , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Toshikazu Ueki , Takaharu Ishizuka , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F9/30
CPC分类号： G06F12/0813 , G06F12/1072
摘要： A multiprocessor system includes a judging unit judging whether a read command inputted to a global address crossbar is a read command to a memory on an own system board, an executing unit speculatively executing, when the judging unit judges that the read command is a read command to the memory on the own system board, the read command before global access based on an address notified from the global address crossbar, a setting unit setting for queuing data read from the memory in a data queue provided on a CPU without queuing the data in a data queue provided on the memory, and an instructing unit instructing, based on notification from the global address crossbar, the data queue provided on the CPU to discard the data or transmit the data to the CPU.
摘要翻译：多处理器系统包括判断单元，判断单元判断输入到全局地址交叉开关的读取命令是否是对自身系统板上的存储器的读取命令，当判断单元判断读取命令是读取命令时，执行单元推测执行基于从全局地址交叉开关通知的地址，在全局访问之前的读取命令，在CPU上提供的数据队列中从存储器读取数据的设置单元设置，而不排队数据设置在存储器上的数据队列，以及指示单元，根据来自全局地址交叉开关的通知指示CPU上提供的数据队列，丢弃数据或将数据发送到CPU。

9. 发明申请

US20110320683A1 Information processing system, resynchronization method and storage medium storing firmware program 审中-公开
标题翻译：信息处理系统，再同步方法和存储固件程序的存储介质
公开(公告)号：US20110320683A1
公开(公告)日：2011-12-29
申请号：US13137671
申请日：2011-09-01
申请人： Toshikazu Ueki , Makoto Hataida , Takaharu Ishizuka , Yuka Hosokawa , Takashi Yamamoto , Kenta Sato
发明人： Toshikazu Ueki , Makoto Hataida , Takaharu Ishizuka , Yuka Hosokawa , Takashi Yamamoto , Kenta Sato
IPC分类号： G06F12/00
CPC分类号： G06F11/1441 , G06F11/16
摘要： An information processing system includes sets of multiple processors performing processing synchronously. The system includes: a ROM storing a firmware program activating the processors to a synchronized state; a RAM defined by one address map; a firmware copying section copying the firmware program in the ROM to the RAM, on system boot; and a RAM address register storing an address of the RAM and of a copy destination of the firmware program. The system further includes: a RAM address storing section storing the address of the RAM and of the copy destination of the firmware program; a loss-of-synchronism detection section detecting loss of synchronism of the processors; and an address replacing section referring to the RAM address register upon detection of the loss of synchronism, thereby replacing an address for reading the stored firmware program, with the address of the RAM and of the copy destination of the firmware program.
摘要翻译：信息处理系统包括同时执行处理的多个处理器的集合。该系统包括：ROM，存储将处理器激活到同步状态的固件程序; 由一个地址图定义的RAM; 固件复制部分将系统启动时将ROM中的固件程序复制到RAM; 以及存储RAM的地址和固件程序的复制目的地的RAM地址寄存器。该系统还包括：存储RAM的地址和固件程序的复制目的地的RAM地址存储部分; 检测处理器的同步丢失的失去同步检测部分; 以及在检测到同步丢失时参考RAM地址寄存器的地址替换部分，从而用RAM的地址和固件程序的复制目的地替换用于读取所存储的固件程序的地址。

10. 发明授权

US08065566B2 Node device, control device, control method and control program 有权
标题翻译：节点装置，控制装置，控制方法和控制程序
公开(公告)号：US08065566B2
公开(公告)日：2011-11-22
申请号：US11785759
申请日：2007-04-19
申请人： Takashi Yamamoto , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takashi Yamamoto , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F11/10
CPC分类号： H04L1/004 , H04L1/0082 , H04L2001/0097
摘要： A control device managing a plurality of nodes transmitting and receiving data containing an error correcting code, comprises means accepting, when any one of the nodes detects an uncorrectable error from the data containing the error correcting code, a signal transmitted by the node detecting the error, means judging from a record of the detection of a first node, when accepting the signal from a second node receiving data transmitted by the first node, whether or not the first node has detected the uncorrectable error from the data transmitted to the second node, and means stopping, when the first node has detected the uncorrectable error from the data transmitted to the second node, a process attributed to the acceptance of the signal from the second node.
摘要翻译：管理发送和接收包含纠错码的数据的多个节点的控制装置包括当任何一个节点从包含纠错码的数据中检测到不可校正的错误时，接收由检测到错误的节点发送的信号从第一节点接收到的数据接收来自第二节点的信号，从第一节点的检测记录中判断第一节点是否从发送到第二节点的数据检测到不可校正的错误，并且意味着当第一节点从发送到第二节点的数据中检测到不可校正的错误时，停止归因于来自第二节点的信号的接受的处理。

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