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1. 发明授权

US08576000B2 3D chip stack skew reduction with resonant clock and inductive coupling 有权
标题翻译：具有谐振时钟和电感耦合的3D芯片堆栈倾斜减少
公开(公告)号：US08576000B2
公开(公告)日：2013-11-05
申请号：US13217349
申请日：2011-08-25
申请人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
发明人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
IPC分类号： H01L25/00
CPC分类号： H03L7/00 , G06F1/10 , H01L2924/0002 , H01L2924/00
摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.
摘要翻译：提供了一种时钟分配网络，用于在具有两个或更多个层的3D芯片堆栈内同步全局时钟信号。时钟分配网络包括多个时钟分配电路，每个时钟分配电路被布置在两个或更多个层中的相应一个上，用于将全局时钟信号提供给各种芯片位置。多个时钟分配电路中的每一个包括用于为时钟分配网络提供层间层耦合的谐振电路。谐振电路包括至少一个电容器和至少一个电感器。

2. 发明授权

US07189640B2 Method of forming damascene structures 有权
标题翻译：形成镶嵌结构的方法
公开(公告)号：US07189640B2
公开(公告)日：2007-03-13
申请号：US10904877
申请日：2004-12-02
申请人： Chun-Jen Weng , Yu-Shiang Lin , Chih-Yi Cheng
发明人： Chun-Jen Weng , Yu-Shiang Lin , Chih-Yi Cheng
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76832
摘要： A method of forming damascene structures. A substrate including a dielectric layer thereon is provided. The dielectric layer has a plurality of via holes. A gap filler is formed into each via hole. Subsequently, a first anti-reflective coating (ARC) film and a second ARC film are consecutively formed on the dielectric layer. A photoresist pattern for defining a trench pattern is formed on the second ARC film. Following that, an etching process is performed to remove an upper part of the dielectric layer left uncovered by the photoresist pattern to form a plurality of trenches.
摘要翻译：一种形成镶嵌结构的方法。提供了包括其上的介电层的基板。电介质层具有多个通孔。在每个通孔中形成间隙填料。随后，在电介质层上连续地形成第一抗反射涂层（ARC）膜和第二ARC膜。在第二ARC膜上形成用于限定沟槽图案的光致抗蚀剂图案。之后，进行蚀刻处理以去除由光致抗蚀剂图案未覆盖的电介质层的上部以形成多个沟槽。

3. 发明申请

US20060121730A1 METHOD OF FORMING DAMASCENE STRUCTURES 有权
标题翻译：形成大气结构的方法
公开(公告)号：US20060121730A1
公开(公告)日：2006-06-08
申请号：US10904877
申请日：2004-12-02
申请人： Chun-Jen Weng , Yu-Shiang Lin , Chih-Yi Cheng
发明人： Chun-Jen Weng , Yu-Shiang Lin , Chih-Yi Cheng
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76832
摘要： A substrate including a dielectric layer thereon is provided. The dielectric layer has a plurality of via holes. A gap filler is formed into each via hole. Subsequently, a first anti-reflective coating (ARC) film and a second ARC film are consecutively formed on the dielectric layer. A photoresist pattern for defining a trench pattern is formed on the second ARC film. Following that, an etching process is performed to remove an upper part of the dielectric layer left uncovered by the photoresist pattern to form a plurality of trenches.
摘要翻译：提供了包括其上的介电层的基板。电介质层具有多个通孔。在每个通孔中形成间隙填料。随后，在电介质层上连续地形成第一抗反射涂层（ARC）膜和第二ARC膜。在第二ARC膜上形成用于限定沟槽图案的光致抗蚀剂图案。之后，进行蚀刻处理以去除由光致抗蚀剂图案未覆盖的电介质层的上部以形成多个沟槽。

4. 发明授权

US08587357B2 AC supply noise reduction in a 3D stack with voltage sensing and clock shifting 有权
标题翻译：在具有电压感测和时钟偏移的3D堆叠中的交流电源降噪
公开(公告)号：US08587357B2
公开(公告)日：2013-11-19
申请号：US13217406
申请日：2011-08-25
申请人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
发明人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
IPC分类号： H03K5/00 , H03K3/00
CPC分类号： G06F1/10 , G06F1/26 , H01L25/0657 , H01L2224/16145
摘要： There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.
摘要翻译：提供了一种具有两层或多层的3D芯片堆叠的交流电源降噪器。每个层具有多个配电电路中的相应一个和布置在其上的多个时钟分配电路中的相应一个。交流电源降噪器包括多个电压下降传感器和多个偏斜调整器。多个电压下降传感器用于检测多个配电电路中的交流电源噪声。一个或多个电压下降传感器分别布置在至少一些层上。多个偏斜调整器用于响应于交流电源噪声的量来延迟由多个时钟分配电路提供的一个或多个时钟信号。每个偏斜调节器分别布置在至少一些层上。

5. 发明申请

US20130049824A1 3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUPLING 有权
公开(公告)号：US20130049824A1
公开(公告)日：2013-02-28
申请号：US13217349
申请日：2011-08-25
申请人： JAE-JOON KIM , YU-SHIANG LIN , LIANG-TECK PANG , JOEL A. SILBERMAN
发明人： JAE-JOON KIM , YU-SHIANG LIN , LIANG-TECK PANG , JOEL A. SILBERMAN
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , G06F1/10 , H01L2924/0002 , H01L2924/00
摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.

6. 发明申请

US20130018519A1 NETWORK POWER SUPPLY CONTROL SYSTEM, NETWORK POWER SUPPLY EQUIPMENT AND NETWORK POWER DEVICE THEREOF 审中-公开
标题翻译：网络电源控制系统，网络电源设备及其网络电源设备
公开(公告)号：US20130018519A1
公开(公告)日：2013-01-17
申请号：US13546262
申请日：2012-07-11
申请人： Yu-Shiang LIN
发明人： Yu-Shiang LIN
IPC分类号： G06F1/26
CPC分类号： H04L12/10
摘要： A network power supply control system is applicable to a network power supply equipment (PSE) and a network power device (PD) connected through a network cable. A signal generator is disposed on the network PSE for generating and combining an operating signal with a power signal provided by the network PSE. A signal analyzer is disposed on the network PD for extracting the operating signal from the power signal received by the network PD and controlling a load circuit of the network PD according to the operating signal. Alternatively, the signal generator is disposed on the PD and sends a operating signal according to a state of the load circuit and combines the operating signal with a return power signal returned by the network PD, and the signal analyzer is disposed on the PSE for extracting the operating signal from the return power signal received by the network PSE.
摘要翻译：网络电源控制系统适用于通过网络电缆连接的网络电源设备（PSE）和网络电源设备（PD）。信号发生器设置在网络PSE上，用于产生并组合操作信号与由网络PSE提供的功率信号。信号分析器设置在网络PD上，用于从网络PD接收的功率信号中提取操作信号，并根据操作信号控制网络PD的负载电路。或者，信号发生器设置在PD上，并根据负载电路的状态发送操作信号，并将操作信号与由网络PD返回的返回功率信号相组合，信号分析器设置在PSE上，用于提取来自由网络PSE接收的返回功率信号的操作信号。

7. 发明授权

US08466739B2 3D chip stack skew reduction with resonant clock and inductive coupling 有权
公开(公告)号：US08466739B2
公开(公告)日：2013-06-18
申请号：US13607089
申请日：2012-09-07
申请人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
发明人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
IPC分类号： H01L25/00
CPC分类号： H03L7/00 , G06F1/10 , H01L2924/0002 , H01L2924/00
摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.

8. 发明申请

US20130049828A1 AC SUPPLY NOISE REDUCTION IN A 3D STACK WITH VOLTAGE SENSING AND CLOCK SHIFTING 有权
标题翻译：在具有电压感测和时钟转换的3D堆叠中的交流电噪声减少
公开(公告)号：US20130049828A1
公开(公告)日：2013-02-28
申请号：US13217406
申请日：2011-08-25
申请人： JAE-JOON KIM , YU-SHIANG LIN , LIANG-TECK PANG , JOEL A. SILBERMAN
发明人： JAE-JOON KIM , YU-SHIANG LIN , LIANG-TECK PANG , JOEL A. SILBERMAN
IPC分类号： H03L7/06
CPC分类号： G06F1/10 , G06F1/26 , H01L25/0657 , H01L2224/16145
摘要： There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.
摘要翻译：提供了一种具有两层或多层的3D芯片堆叠的交流电源降噪器。每个层具有多个配电电路中的相应一个和布置在其上的多个时钟分配电路中的相应一个。交流电源降噪器包括多个电压下降传感器和多个偏斜调整器。多个电压下降传感器用于检测多个配电电路中的交流电源噪声。一个或多个电压下降传感器分别布置在至少一些层上。多个偏斜调整器用于响应于交流电源噪声的量来延迟由多个时钟分配电路提供的一个或多个时钟信号。每个偏斜调节器分别布置在至少一些层上。

9. 发明申请

US20130049826A1 3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUPLING 有权
标题翻译： 3D芯片堆叠减少与谐振时钟和电感耦合
公开(公告)号：US20130049826A1
公开(公告)日：2013-02-28
申请号：US13607089
申请日：2012-09-07
申请人： JAE-JOON KIM , YU-SHIANG LIN , LIANG-TECK PANG , JOEL A. SILBERMAN
发明人： JAE-JOON KIM , YU-SHIANG LIN , LIANG-TECK PANG , JOEL A. SILBERMAN
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , G06F1/10 , H01L2924/0002 , H01L2924/00
摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.
摘要翻译：提供了一种时钟分配网络，用于在具有两个或更多个层的3D芯片堆栈内同步全局时钟信号。时钟分配网络包括多个时钟分配电路，每个时钟分配电路被布置在两个或更多个层中的相应一个上，用于将全局时钟信号提供给各种芯片位置。多个时钟分配电路中的每一个包括用于为时钟分配网络提供层间层耦合的谐振电路。谐振电路包括至少一个电容器和至少一个电感器。

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