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1. 发明授权

US08519735B2 Programming the behavior of individual chips or strata in a 3D stack of integrated circuits 有权
公开(公告)号：US08519735B2
公开(公告)日：2013-08-27
申请号：US13217734
申请日：2011-08-25
申请人： Liang-Teck Pang , Joel A. Silberman , Matthew R. Wordeman
发明人： Liang-Teck Pang , Joel A. Silberman , Matthew R. Wordeman
IPC分类号： H03K19/00
CPC分类号： G01R31/318558 , G01R31/318513 , G01R31/318572 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.

2. 发明授权

US08466739B2 3D chip stack skew reduction with resonant clock and inductive coupling 有权
公开(公告)号：US08466739B2
公开(公告)日：2013-06-18
申请号：US13607089
申请日：2012-09-07
申请人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
发明人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
IPC分类号： H01L25/00
CPC分类号： H03L7/00 , G06F1/10 , H01L2924/0002 , H01L2924/00
摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.

3. 发明申请

US20130049828A1 AC SUPPLY NOISE REDUCTION IN A 3D STACK WITH VOLTAGE SENSING AND CLOCK SHIFTING 有权
标题翻译：在具有电压感测和时钟转换的3D堆叠中的交流电噪声减少
公开(公告)号：US20130049828A1
公开(公告)日：2013-02-28
申请号：US13217406
申请日：2011-08-25
申请人： JAE-JOON KIM , YU-SHIANG LIN , LIANG-TECK PANG , JOEL A. SILBERMAN
发明人： JAE-JOON KIM , YU-SHIANG LIN , LIANG-TECK PANG , JOEL A. SILBERMAN
IPC分类号： H03L7/06
CPC分类号： G06F1/10 , G06F1/26 , H01L25/0657 , H01L2224/16145
摘要： There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.
摘要翻译：提供了一种具有两层或多层的3D芯片堆叠的交流电源降噪器。每个层具有多个配电电路中的相应一个和布置在其上的多个时钟分配电路中的相应一个。交流电源降噪器包括多个电压下降传感器和多个偏斜调整器。多个电压下降传感器用于检测多个配电电路中的交流电源噪声。一个或多个电压下降传感器分别布置在至少一些层上。多个偏斜调整器用于响应于交流电源噪声的量来延迟由多个时钟分配电路提供的一个或多个时钟信号。每个偏斜调节器分别布置在至少一些层上。

4. 发明申请

US20130049826A1 3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUPLING 有权
标题翻译： 3D芯片堆叠减少与谐振时钟和电感耦合
公开(公告)号：US20130049826A1
公开(公告)日：2013-02-28
申请号：US13607089
申请日：2012-09-07
申请人： JAE-JOON KIM , YU-SHIANG LIN , LIANG-TECK PANG , JOEL A. SILBERMAN
发明人： JAE-JOON KIM , YU-SHIANG LIN , LIANG-TECK PANG , JOEL A. SILBERMAN
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , G06F1/10 , H01L2924/0002 , H01L2924/00
摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.
摘要翻译：提供了一种时钟分配网络，用于在具有两个或更多个层的3D芯片堆栈内同步全局时钟信号。时钟分配网络包括多个时钟分配电路，每个时钟分配电路被布置在两个或更多个层中的相应一个上，用于将全局时钟信号提供给各种芯片位置。多个时钟分配电路中的每一个包括用于为时钟分配网络提供层间层耦合的谐振电路。谐振电路包括至少一个电容器和至少一个电感器。

5. 发明授权

US08127116B2 Dependency matrix with reduced area and power consumption 失效
标题翻译：具有减少面积和功耗的依赖矩阵
公开(公告)号：US08127116B2
公开(公告)日：2012-02-28
申请号：US12417768
申请日：2009-04-03
申请人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
发明人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.
摘要翻译：具有依赖矩阵的处理器包括包括多个第一单元的第一阵列。第二阵列耦合到第一阵列并且包括多个第二单元。第一个写入端口耦合到第一个阵列和第二个阵列，并写入第一个阵列和第二个阵列。第一读端口耦合到第一阵列和第二阵列，并从第一阵列和第二阵列读取。第二个读取端口耦合到第一个数组并从第一个数组读取。第二个写入端口耦合到第二个读取端口，从第二个读取端口读取并写入第二个数据。

6. 发明申请

US20080195850A1 Method and System for Restoring Register Mapper States for an Out-Of-Order Microprocessor 失效
标题翻译：用于为无序微处理器恢复寄存器映射器状态的方法和系统
公开(公告)号：US20080195850A1
公开(公告)日：2008-08-14
申请号：US11674754
申请日：2007-02-14
申请人： Christopher M. Abernathy , Mary D. Brown , Dung Q. Nguyen , Joel A. Silberman
发明人： Christopher M. Abernathy , Mary D. Brown , Dung Q. Nguyen , Joel A. Silberman
IPC分类号： G06F9/38
CPC分类号： G06F9/3863 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3885
摘要： A method of restoring register mapper states for an out-of-order microprocessor. A processor maps a logical register to a physical register in a map table in response to a first instruction. Instruction sequencing logic records a second speculatively executed instruction as a most recently dispatched instruction in the map table when the second instruction maps the same logical register of the first instruction. The instruction sequencing logic sets an evictor instruction tag (ITAG) of the first instruction in the map table when the second instruction maps a same logical register of the first instruction. The instruction sequencing logic detects mispredicted speculative instructions, determines which instructions in the map table were dispatched prior to the mispredicted speculative instructions, and restores the map table to a state prior to the mispredicted speculative instructions by utilizing the evictor ITAG to restore one or more A bits in the map table data structure.
摘要翻译：一种恢复无序微处理器的寄存器映射器状态的方法。处理器响应于第一指令将逻辑寄存器映射到地图表中的物理寄存器。当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑将第二推测执行指令记录为映射表中最近调度的指令。当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑设置映射表中的第一指令的撤销指令标签（ITAG）。指令排序逻辑检测误预测的推测指令，确定映射表中的哪些指令在误预测的推测指令之前被分派，并且通过利用驱逐者ITAG恢复一个或多个A，将映射表恢复到误预测的推测指令之前的状态位图中的数据结构。

7. 发明授权

US07079409B2 Apparatus and method for power savings in high-performance CAM structures 失效
公开(公告)号：US07079409B2
公开(公告)日：2006-07-18
申请号：US10899358
申请日：2004-07-26
申请人： Chiaming Chai , Michael T. Phan , Joel A. Silberman , Carmen C. Sloan
发明人： Chiaming Chai , Michael T. Phan , Joel A. Silberman , Carmen C. Sloan
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： This invention reduces power consumed during CAM search operations in a CAM/RAM structure utilizing a segmented match line structure. This device is useful when it is known that a portion or portions of the compare data inputs vary infrequently. The apparatus sometimes may be referred to as local match line hold latch, and is a device that stores the value of a local match line comparison result the first time that a search operation occurs, and will stay at that value until the value of the compare data in of the local match line changes.

8. 发明授权

US08576000B2 3D chip stack skew reduction with resonant clock and inductive coupling 有权
标题翻译：具有谐振时钟和电感耦合的3D芯片堆栈倾斜减少
公开(公告)号：US08576000B2
公开(公告)日：2013-11-05
申请号：US13217349
申请日：2011-08-25
申请人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
发明人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
IPC分类号： H01L25/00
CPC分类号： H03L7/00 , G06F1/10 , H01L2924/0002 , H01L2924/00
摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.
摘要翻译：提供了一种时钟分配网络，用于在具有两个或更多个层的3D芯片堆栈内同步全局时钟信号。时钟分配网络包括多个时钟分配电路，每个时钟分配电路被布置在两个或更多个层中的相应一个上，用于将全局时钟信号提供给各种芯片位置。多个时钟分配电路中的每一个包括用于为时钟分配网络提供层间层耦合的谐振电路。谐振电路包括至少一个电容器和至少一个电感器。

9. 发明申请

US20100257336A1 Dependency Matrix with Reduced Area and Power Consumption 失效
标题翻译：具有减小面积和功耗的依赖矩阵
公开(公告)号：US20100257336A1
公开(公告)日：2010-10-07
申请号：US12417768
申请日：2009-04-03
申请人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
发明人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
IPC分类号： G06F9/44 , G06F15/00 , G06F9/30
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.
摘要翻译：具有依赖矩阵的处理器包括包括多个第一单元的第一阵列。第二阵列耦合到第一阵列并且包括多个第二单元。第一个写入端口耦合到第一个阵列和第二个阵列，并写入第一个阵列和第二个阵列。第一读端口耦合到第一阵列和第二阵列，并从第一阵列和第二阵列读取。第二个读取端口耦合到第一个数组并从第一个数组读取。第二个写入端口耦合到第二个读取端口，从第二个读取端口读取并写入第二个数据。

10. 发明授权

US07170316B2 Programmable logic array latch 失效
标题翻译：可编程逻辑阵列锁存器
公开(公告)号：US07170316B2
公开(公告)日：2007-01-30
申请号：US10982018
申请日：2004-11-05
申请人： Sang Hoo Dhong , Brian K. Flachs , Joel A. Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Brian K. Flachs , Joel A. Silberman , Osamu Takahashi
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1772
摘要： A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array.
摘要翻译：公开了一种可编程逻辑阵列（PLA）锁存器。 PLA锁存器包括第一逻辑阵列，第二逻辑阵列和仅一个输出锁存器。第二逻辑阵列耦合到第一逻辑阵列。输出锁存器耦合到第二逻辑阵列。

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