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1. 发明申请

US20110128072A1 REPAIR CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权
标题翻译：维修电路和半导体器件包括它们
公开(公告)号：US20110128072A1
公开(公告)日：2011-06-02
申请号：US12836443
申请日：2010-07-14
申请人： Min Seok CHOI , Young Jun Ku
发明人： Min Seok CHOI , Young Jun Ku
IPC分类号： H01L25/00
CPC分类号： H01L22/22 , G06F2213/0038 , H01L23/481 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： A repair circuit of a semiconductor apparatus includes a transmission control unit configured to generate first through nth (n is an integer equal to or greater than 2) control signals in response to a repair information signal, and enable all mth through nth control signals when the repair information signal indicating an mth (m is an integer equal to or greater than 1 and equal to or less than n) TSV is inputted; transmission units configured to allocate transmission paths for first through nth signals to first through nth TSVs and a repair TSV in response to the first through nth control signals; and receiving units configured to receive the signals transmitted from the first through nth TSVs and the repair TSV in response to the first through nth control signals.
摘要翻译：半导体装置的修复电路包括发送控制单元，被配置为响应于修复信息信号产生第一至第n（n是等于或大于2的整数）控制信号，并且当第二至第N控制信号输入指示第m（m为1以上且等于或小于n的整数）TSV的修复信息信号; 传输单元，被配置为响应于第一至第N控制信号，将第一到第n个信号的传输路径分配到第一到第n个TSV和修复TSV; 以及接收单元，被配置为响应于第一至第N控制信号接收从第一至第TSV和修复TSV发送的信号。

2. 发明授权

US08339879B2 Repair circuit and semiconductor apparatus including the same 有权
标题翻译：修理电路和包括其的半导体装置
公开(公告)号：US08339879B2
公开(公告)日：2012-12-25
申请号：US12836443
申请日：2010-07-14
申请人： Min Seok Choi , Young Jun Ku
发明人： Min Seok Choi , Young Jun Ku
IPC分类号： G11C7/00
CPC分类号： H01L22/22 , G06F2213/0038 , H01L23/481 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： A repair circuit of a semiconductor apparatus includes a transmission control unit configured to generate first through nth (n is an integer equal to or greater than 2) control signals in response to a repair information signal, and enable all mth through nth control signals when the repair information signal indicating an mth (m is an integer equal to or greater than 1 and equal to or less than n) TSV is inputted; transmission units configured to allocate transmission paths for first through nth signals to first through nth TSVs and a repair TSV in response to the first through nth control signals; and receiving units configured to receive the signals transmitted from the first through nth TSVs and the repair TSV in response to the first through nth control signals.
摘要翻译：半导体装置的修复电路包括发送控制单元，被配置为响应于修复信息信号产生第一至第n（n是等于或大于2的整数）控制信号，并且当第二至第N控制信号输入指示第m（m为1以上且等于或小于n的整数）TSV的修复信息信号; 传输单元，被配置为响应于第一至第N控制信号，将第一到第n个信号的传输路径分配到第一到第n个TSV和修复TSV; 以及接收单元，被配置为响应于第一至第N控制信号接收从第一至第TSV和修复TSV发送的信号。

3. 发明授权

US08411478B2 Three-dimensional stacked semiconductor integrated circuit 有权
标题翻译：三维堆叠半导体集成电路
公开(公告)号：US08411478B2
公开(公告)日：2013-04-02
申请号：US12970907
申请日：2010-12-16
申请人： Tae Sik Yun , Young Jun Ku
发明人： Tae Sik Yun , Young Jun Ku
IPC分类号： G11C5/06
CPC分类号： H01L25/18 , G11C5/02 , G11C5/06 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments of a three-dimensional, stacked semiconductor integrated circuit are disclosed. In one exemplary embodiment, the circuit may include a master slice, a plurality of slave slices, and a plurality of through-silicon vias for connecting the master slice to the plurality of slave slices. At least one of the plurality of through-silicon vias may be configured to transmit an operation control signal from the master slice to the plurality of slave slices. The at least one of the plurality of through-silicon vias is configured to be shared by the plurality of slave slices.
摘要翻译：公开了三维叠层半导体集成电路的各种实施例。在一个示例性实施例中，电路可以包括主切片，多个从切片以及用于将主切片连接到多个从切片的多个穿硅通孔。多个穿硅通孔中的至少一个可以被配置为将操作控制信号从主切片发送到多个从切片。多个通硅通孔中的至少一个被配置为由多个从切片共享。

4. 发明申请

US20110267898A1 SEMICONDUCTOR MEMORY APPARATUS 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20110267898A1
公开(公告)日：2011-11-03
申请号：US12841053
申请日：2010-07-21
申请人： Tae Sik Yun , Young Jun Ku
发明人： Tae Sik Yun , Young Jun Ku
IPC分类号： G11C7/10
CPC分类号： G11C7/1066
摘要： A semiconductor memory apparatus includes a clock transmission unit configured to selectively output a data strobe clock signal or a phase correction clock signal based on an operation mode, and a data latch unit configured to latch a plurality of data signals under a control of a clock signal which is outputted from the clock transmission unit.
摘要翻译：一种半导体存储装置，包括：时钟发送单元，被配置为基于操作模式选择性地输出数据选通时钟信号或相位校正时钟信号;以及数据锁存单元，被配置为在时钟信号的控制下锁存多个数据信号其从时钟发送单元输出。

5. 发明授权

US07940074B2 Data transmission circuit and semiconductor apparatus including the same 有权
标题翻译：数据传输电路和包括其的半导体装置
公开(公告)号：US07940074B2
公开(公告)日：2011-05-10
申请号：US12650433
申请日：2009-12-30
申请人： Young Jun Ku
发明人： Young Jun Ku
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/003
CPC分类号： H04L25/0272 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A data transmission circuit includes a data transmission unit and a data receiving unit. The data transmission unit generates transmission data based on first chip data and transmit the transmission data via a Through Silicon Via (TSV). The data receiving unit differentially amplifies the transmission data with respect to a reference voltage to generate second chip data.
摘要翻译：数据传输电路包括数据传输单元和数据接收单元。数据发送单元基于第一芯片数据生成发送数据，并且经由硅通路（TSV）发送发送数据。数据接收单元相对于参考电压差分地放大发送数据，以产生第二芯片数据。

6. 发明授权

US08456931B2 Data transmission device 有权
标题翻译：数据传输设备
公开(公告)号：US08456931B2
公开(公告)日：2013-06-04
申请号：US12947298
申请日：2010-11-16
申请人： Young Jun Ku
发明人： Young Jun Ku
IPC分类号： G11C7/00
CPC分类号： G11C29/48 , G11C29/1201
摘要： A data transmission device in a semiconductor memory apparatus receives input data via a local data input/output line and output s the input data on a plurality of global data input/output lines. The data transmission device includes a write data generation block configured to receive the input data and test data and output one of input data and test data as write data in response to an activation of a test enable signal, and a loading block configured to apply the write data to one of the plurality of global data input/output lines in response to an enable signal.
摘要翻译：半导体存储装置中的数据传输装置经由本地数据输入/输出线接收输入数据，并输出多个全局数据输入/输出线上的输入数据。数据传输装置包括写数据生成块，其被配置为响应于激活测试使能信号而接收输入数据和测试数据并输出输入数据和测试数据之一作为写入数据;以及加载块，响应于使能信号将数据写入多个全局数据输入/输出线中的一个。

7. 发明授权

US08922237B2 Semiconductor integrated circuit with testing and repairing via 有权
标题翻译：半导体集成电路通过测试和修复
公开(公告)号：US08922237B2
公开(公告)日：2014-12-30
申请号：US13604519
申请日：2012-09-05
申请人： Young Jun Ku
发明人： Young Jun Ku
IPC分类号： G01R31/02
CPC分类号： G01R31/318513 , G01R31/2853 , G01R31/31717 , H01L22/22 , H01L23/481 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor integrated circuit includes a plurality of semiconductor chips coupled to one another through vias, wherein a lowermost semiconductor chip of the plurality of semiconductor chips is configured to generate a first test pulse signal and transmit the first test pulse signal through the via, an uppermost semiconductor chip of the plurality of semiconductor chips is configured to generate a second test pulse signal while substantially maintaining a time difference with the first test pulse signal, and to transmit the second test pulse signal through the via, and the plurality of semiconductor chips are configured to generate test result signals for determining whether the vias are defective in response to the first test pulse signal and the second test pulse signal.
摘要翻译：半导体集成电路包括通过通孔彼此耦合的多个半导体芯片，其中多个半导体芯片中的最下半导体芯片被配置为产生第一测试脉冲信号，并通过通孔传输第一测试脉冲信号，最上面的多个半导体芯片的半导体芯片被配置为产生第二测试脉冲信号，同时基本上保持与第一测试脉冲信号的时间差，并且通过通孔传输第二测试脉冲信号，并且配置多个半导体芯片以产生用于响应于第一测试脉冲信号和第二测试脉冲信号来确定通孔是否有缺陷的测试结果信号。

8. 发明授权

US07545189B2 Delayed locked loop circuit 有权
标题翻译：延迟锁定回路电路
公开(公告)号：US07545189B2
公开(公告)日：2009-06-09
申请号：US12098534
申请日：2008-04-07
申请人： Young Jun Ku
发明人： Young Jun Ku
IPC分类号： H03L7/06
CPC分类号： H03L7/0802 , H03L7/0805 , H03L7/0812
摘要： A Delayed Locked Loop Circuit of DLL comprises a buffer that receives a power-down signal and an inverted signal of a first clock signal; first and second delay lines an output device that outputs signals corresponding to the output signals of the first and second delay lines respectively; a replica delay unit, a phase comparator for comparing a phase difference between the output signal of the second buffer and the output signal of the replica delay unit; and a delay line controller for controlling delay times of the first delay line and the second delay line by corresponding to a comparison result of the phase comparator. The DLL circuit is configured such that the first and second buffers are disabled when the power-down mode entry notifying signal corresponding to a power-down mode is provided.
摘要翻译： DLL的延迟锁定环路电路包括接收掉电信号和第一时钟信号的反相信号的缓冲器; 第一和第二延迟线，分别输出与第一和第二延迟线的输出信号对应的信号的输出装置; 复制延迟单元，用于比较第二缓冲器的输出信号和复制延迟单元的输出信号之间的相位差的相位比较器; 以及延迟线控制器，用于通过对应于相位比较器的比较结果来控制第一延迟线和第二延迟线的延迟时间。配置DLL电路，使得当提供与掉电模式相对应的掉电模式进入通知信号时，禁用第一和第二缓冲器。

9. 发明授权

US07405603B2 Delayed Locked Loop Circuit 失效
标题翻译：延迟锁定回路电路
公开(公告)号：US07405603B2
公开(公告)日：2008-07-29
申请号：US11544283
申请日：2006-10-06
申请人： Young Jun Ku
发明人： Young Jun Ku
IPC分类号： H03L7/06
CPC分类号： H03L7/0802 , H03L7/0805 , H03L7/0812
摘要： A Delayed Locked Loop Circuit of DLL comprises a buffer that receives a power-down signal and an inverted signal of a first clock signal; first and second delay lines an output device that outputs signals corresponding to the output signals of the first and second delay lines respectively; a replica delay unit, a phase comparator for comparing a phase difference between the output signal of the second buffer and the output signal of the replica delay unit; and a delay line controller for controlling delay times of the first delay line and the second delay line by corresponding to a comparison result of the phase comparator. The DLL circuit is configured such that the first and second buffers are disabled when the power-down mode entry notifying signal corresponding to a power-down mode is provided.
摘要翻译： DLL的延迟锁定环路电路包括接收掉电信号和第一时钟信号的反相信号的缓冲器; 第一和第二延迟线，分别输出与第一和第二延迟线的输出信号对应的信号的输出装置; 复制延迟单元，用于比较第二缓冲器的输出信号和复制延迟单元的输出信号之间的相位差的相位比较器; 以及延迟线控制器，用于通过对应于相位比较器的比较结果来控制第一延迟线和第二延迟线的延迟时间。配置DLL电路，使得当提供与掉电模式相对应的掉电模式进入通知信号时，禁用第一和第二缓冲器。

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