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1. 发明授权

US08310005B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US08310005B2
公开(公告)日：2012-11-13
申请号：US13317781
申请日：2011-10-28
申请人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
发明人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/66734
摘要： A semiconductor device includes a semiconductor layer, a first diffused region formed in the semiconductor layer, a second diffused region formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode disposed in the trench, a top surface of the gate electrode being lower than a top surface of the semiconductor layer and sagging downwards in a center thereof, a non-doped silicate glass film disposed in the trench and formed over the gate electrode, a top surface of the silicate glass film sagging downwards in a center thereof, an oxide film disposed in the trench and formed over the non-doped silicate glass film, a top surface of the oxide film sagging downwards in a center, and a source electrode formed over the semiconductor layer so that the source electrode contacts the first and second diffusion regions, and the oxide film at the top surface thereof.

2. 发明申请

US20080135921A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080135921A1
公开(公告)日：2008-06-12
申请号：US11984043
申请日：2007-11-13
申请人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
发明人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
IPC分类号： H01L29/788 , H01L21/76
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/66734
摘要： An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate trench and a polysilicon is formed in the gate trench with the gate insulator interposed therebetween. An HTO film is formed on the surface of the polysilicon and the n− epitaxial layer. At this time, an ion plantation is performed to the epitaxial layer through the HTO film. Hence, a p diffused base layer, an n+ diffused source layer, an n+ diffused source layer is formed. A CVD oxide film is formed on the HTO film. After a BPSG having flowability is deposited on the CVD oxide film, the BPSG film is planarized with a heat treatment of 900-1100 degree Celsius.
摘要翻译：通过外延生长在n +半导体衬底上形成外延层。栅极沟槽形成在栅极沟槽的表面，使得栅极沟槽的底部到达外延层的中间。栅极绝缘体形成在栅极沟槽的内壁上，并且栅极沟槽中形成多晶硅，栅极绝缘体插入其间。在多晶硅和n外延层的表面上形成HTO膜。此时，通过HTO膜对外延层进行离子种植。因此，形成p扩散基极层，n +扩散源极层，n +扩散源极层。在HTO膜上形成CVD氧化膜。在具有流动性的BPSG沉积在CVD氧化物膜上之后，通过900-1100℃的热处理将BPSG膜平坦化。

3. 发明授权

US08072026B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08072026B2
公开(公告)日：2011-12-06
申请号：US12659454
申请日：2010-03-09
申请人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
发明人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
IPC分类号： H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119 , H01L29/00
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/66734
摘要： A semiconductor device, includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a polysilicon formed in the trench with an insulator intervening, a first oxide film formed on the polysilicon so that the first oxide film is buried in the trench, a second oxide film formed on the first oxide film so that the second oxide film is buried in the trench, and a flowable insulator film formed on the second oxide film so that the flowable insulator film is buried in the trench.
摘要翻译：一种半导体器件，包括第二导电类型的半导体层，形成在半导体层中的第一导电类型的第一扩散区域，选择性地形成在第一扩散区域中的第二导电类型的第二扩散区域，形成在半导体层，形成在具有绝缘体的沟槽中的多晶硅，形成在多晶硅上的第一氧化物膜，使得第一氧化物膜被埋在沟槽中，形成在第一氧化物膜上的第二氧化物膜，使得第二氧化物膜被埋在沟槽中，以及形成在第二氧化物膜上的可流动的绝缘膜，使得可流动的绝缘膜被埋在沟槽中。

4. 发明授权

US07947556B2 Method of manufacturing semiconductor apparatus 有权
标题翻译：半导体装置的制造方法
公开(公告)号：US07947556B2
公开(公告)日：2011-05-24
申请号：US12801806
申请日：2010-06-25
申请人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
发明人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/66734
摘要： A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
摘要翻译：一种制造半导体装置的方法包括在半导体层中形成沟槽，在沟槽内部形成栅电极，在沟槽内部的栅电极上形成热氧化膜，在内部的热氧化膜上形成硅酸盐玻璃膜沟槽，在半导体层内部形成体区，并且在身体区域上形成源区。该方法提供了具有减小的通道长度波动和低导通电阻的半导体装置。

5. 发明授权

US07776693B2 Method of manufacturing semiconductor apparatus 失效
标题翻译：半导体装置的制造方法
公开(公告)号：US07776693B2
公开(公告)日：2010-08-17
申请号：US11905078
申请日：2007-09-27
申请人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
发明人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/66734
摘要： A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
摘要翻译：一种制造半导体装置的方法包括在半导体层中形成沟槽，在沟槽内部形成栅电极，在沟槽内部的栅电极上形成热氧化膜，在内部的热氧化膜上形成硅酸盐玻璃膜沟槽，在半导体层内部形成体区，并且在身体区域上形成源区。该方法提供了具有减小的通道长度波动和低导通电阻的半导体装置。

6. 发明授权

US07704827B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07704827B2
公开(公告)日：2010-04-27
申请号：US11984043
申请日：2007-11-13
申请人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
发明人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
IPC分类号： H01L21/8242
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/66734
摘要： An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate trench and a polysilicon is formed in the gate trench with the gate insulator interposed therebetween. An HTO film is formed on the surface of the polysilicon and the n− epitaxial layer. At this time, an ion plantation is performed to the epitaxial layer through the HTO film. Hence, a p diffused base layer, an n+ diffused source layer, an n+ diffused source layer is formed. A CVD oxide film is formed on the HTO film. After a BPSG having flowability is deposited on the CVD oxide film, the BPSG film is planarized with a heat treatment of 900-1100 degree Celsius.
摘要翻译：通过外延生长在n +半导体衬底上形成外延层。栅极沟槽形成在栅极沟槽的表面，使得栅极沟槽的底部到达外延层的中间。栅极绝缘体形成在栅极沟槽的内壁上，并且栅极沟槽中形成多晶硅，栅极绝缘体插入其间。在多晶硅和n外延层的表面上形成HTO膜。此时，通过HTO膜对外延层进行离子种植。因此，形成p扩散基极层，n +扩散源极层，n +扩散源极层。在HTO膜上形成CVD氧化膜。在具有流动性的BPSG沉积在CVD氧化物膜上之后，通过900-1100摄氏度的热处理将BPSG膜平坦化。

7. 发明申请

US20080081422A1 Method of manufacturing semiconductor apparatus 失效
标题翻译：半导体装置的制造方法
公开(公告)号：US20080081422A1
公开(公告)日：2008-04-03
申请号：US11905078
申请日：2007-09-27
申请人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
发明人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/66734
摘要： A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
摘要翻译：一种制造半导体装置的方法包括在半导体层中形成沟槽，在沟槽内部形成栅电极，在沟槽内部的栅电极上形成热氧化膜，在内部的热氧化膜上形成硅酸盐玻璃膜沟槽，在半导体层内部形成体区，并且在身体区域上形成源区。该方法提供了具有减小的通道长度波动和低导通电阻的半导体装置。

8. 发明申请

US20120043604A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20120043604A1
公开(公告)日：2012-02-23
申请号：US13317781
申请日：2011-10-28
申请人： Yoshimitsu MURASE , Kenya KOBAYASHI , Hideo YAMAMOTO , Atsushi KANEKO
发明人： Yoshimitsu MURASE , Kenya KOBAYASHI , Hideo YAMAMOTO , Atsushi KANEKO
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/66734
摘要： A semiconductor device includes a semiconductor layer, a first diffused region formed in the semiconductor layer, a second diffused region formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode disposed in the trench, a top surface of the gate electrode being lower than a top surface of the semiconductor layer and sagging downwards in a center thereof, a non-doped silicate glass film disposed in the trench and formed over the gate electrode, a top surface of the silicate glass film sagging downwards in a center thereof, an oxide film disposed in the trench and formed over the non-doped silicate glass film, a top surface of the oxide film sagging downwards in a center, and a source electrode formed over the semiconductor layer so that the source electrode contacts the first and second diffusion regions, and the oxide film at the top surface thereof.
摘要翻译：半导体器件包括半导体层，形成在半导体层中的第一扩散区域，形成在第一扩散区域中的第二扩散区域，形成在半导体层中的沟槽，设置在沟槽中的栅极电极，栅电极低于半导体层的顶表面并且在其中心向下流动，设置在沟槽中并形成在栅电极上的未掺杂硅酸盐玻璃膜，硅酸盐玻璃膜的顶表面向下垂下中心，设置在沟槽中并形成在非掺杂硅酸盐玻璃膜上的氧化物膜，氧化膜在中心向下垂的顶表面和形成在半导体层上的源电极，使得源电极接触第一和第二扩散区，以及其顶表面处的氧化物膜。

9. 发明申请

US20100267211A1 Method of manufacturing semiconductor apparatus 有权
公开(公告)号：US20100267211A1
公开(公告)日：2010-10-21
申请号：US12801806
申请日：2010-06-25
申请人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
发明人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/66734
摘要： A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.

10. 发明申请

US20100171172A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100171172A1
公开(公告)日：2010-07-08
申请号：US12659454
申请日：2010-03-09
申请人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
发明人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/66734
摘要： A semiconductor device, includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a polysilicon formed in the trench with an insulator intervening, a first oxide film formed on the polysilicon so that the first oxide film is buried in the trench, a second oxide film formed on the first oxide film so that the second oxide film is buried in the trench, and a flowable insulator film formed on the second oxide film so that the flowable insulator film is buried in the trench.
摘要翻译：一种半导体器件，包括第二导电类型的半导体层，形成在半导体层中的第一导电类型的第一扩散区域，选择性地形成在第一扩散区域中的第二导电类型的第二扩散区域，形成在半导体层，形成在具有绝缘体的沟槽中的多晶硅，形成在多晶硅上的第一氧化物膜，使得第一氧化物膜被埋在沟槽中，形成在第一氧化物膜上的第二氧化物膜，使得第二氧化物膜被埋在沟槽中，以及形成在第二氧化物膜上的可流动的绝缘膜，使得可流动的绝缘膜被埋在沟槽中。

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