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1. 发明授权

US08072026B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08072026B2
公开(公告)日：2011-12-06
申请号：US12659454
申请日：2010-03-09
申请人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
发明人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
IPC分类号： H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119 , H01L29/00
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/66734
摘要： A semiconductor device, includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a polysilicon formed in the trench with an insulator intervening, a first oxide film formed on the polysilicon so that the first oxide film is buried in the trench, a second oxide film formed on the first oxide film so that the second oxide film is buried in the trench, and a flowable insulator film formed on the second oxide film so that the flowable insulator film is buried in the trench.
摘要翻译：一种半导体器件，包括第二导电类型的半导体层，形成在半导体层中的第一导电类型的第一扩散区域，选择性地形成在第一扩散区域中的第二导电类型的第二扩散区域，形成在半导体层，形成在具有绝缘体的沟槽中的多晶硅，形成在多晶硅上的第一氧化物膜，使得第一氧化物膜被埋在沟槽中，形成在第一氧化物膜上的第二氧化物膜，使得第二氧化物膜被埋在沟槽中，以及形成在第二氧化物膜上的可流动的绝缘膜，使得可流动的绝缘膜被埋在沟槽中。

2. 发明授权

US07947556B2 Method of manufacturing semiconductor apparatus 有权
标题翻译：半导体装置的制造方法
公开(公告)号：US07947556B2
公开(公告)日：2011-05-24
申请号：US12801806
申请日：2010-06-25
申请人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
发明人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/66734
摘要： A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
摘要翻译：一种制造半导体装置的方法包括在半导体层中形成沟槽，在沟槽内部形成栅电极，在沟槽内部的栅电极上形成热氧化膜，在内部的热氧化膜上形成硅酸盐玻璃膜沟槽，在半导体层内部形成体区，并且在身体区域上形成源区。该方法提供了具有减小的通道长度波动和低导通电阻的半导体装置。

3. 发明授权

US07893489B2 Semiconductor device having vertical MOSFET 有权
标题翻译：具有垂直MOSFET的半导体器件
公开(公告)号：US07893489B2
公开(公告)日：2011-02-22
申请号：US12081931
申请日：2008-04-23
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L29/0615 , H01L29/0638 , H01L29/0653 , H01L29/402 , H01L29/41766 , H01L29/4238 , H01L29/456 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L2224/0401 , H01L2224/05558 , H01L2224/05572 , H01L2224/0603 , H01L2224/06051 , H01L2224/13021 , H01L2224/131 , H01L2224/1411 , H01L2224/14131 , H01L2224/16 , H01L2924/0002 , H01L2924/04941 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/00014 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： An ON-resistance of a semiconductor device including a vertical MOSFET whose source electrode, gate electrode, and drain electrode are formed on a single surface is reduced. A drift region which is lower in impurity concentration than a drain region is formed over the drain region. A gate trench and a drain contact trench are simultaneously formed in the drift region. A gate insulating film and a gate electrode are formed in the gate trench. A drain electrode is formed in the drain contact trench. A drain contact region which is higher in impurity concentration than the drift region is formed immediately under the drain contact trench.
摘要翻译：包括在单个表面上形成源电极，栅电极和漏电极的垂直MOSFET的半导体器件的导通电阻减小。在漏极区域上形成杂质浓度低于漏极区域的漂移区域。在漂移区域中同时形成栅极沟槽和漏极接触沟槽。栅极绝缘膜和栅电极形成在栅极沟槽中。在漏极接触沟槽中形成漏电极。在漏极接触沟槽的正下方形成杂质浓度高于漂移区域的漏极接触区域。

4. 发明授权

US07776693B2 Method of manufacturing semiconductor apparatus 失效
标题翻译：半导体装置的制造方法
公开(公告)号：US07776693B2
公开(公告)日：2010-08-17
申请号：US11905078
申请日：2007-09-27
申请人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
发明人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/66734
摘要： A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
摘要翻译：一种制造半导体装置的方法包括在半导体层中形成沟槽，在沟槽内部形成栅电极，在沟槽内部的栅电极上形成热氧化膜，在内部的热氧化膜上形成硅酸盐玻璃膜沟槽，在半导体层内部形成体区，并且在身体区域上形成源区。该方法提供了具有减小的通道长度波动和低导通电阻的半导体装置。

5. 发明申请

US20100155833A1 Semiconductor device having vertical type MOSFET and manufacturing method thereof 失效
标题翻译：具有垂直型MOSFET的半导体器件及其制造方法
公开(公告)号：US20100155833A1
公开(公告)日：2010-06-24
申请号：US12591883
申请日：2009-12-03
申请人： Wataru Sumida , Kenya Kobayashi
发明人： Wataru Sumida , Kenya Kobayashi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/2253 , H01L21/26586 , H01L29/0619 , H01L29/0865 , H01L29/0869 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method (and resultant structure) includes forming a semiconductor layer having plural stripe-like trenches, forming a gate electrode buried partially in each of the plural trenches, and introducing an impurity into the semiconductor layer by ion implantation after forming the gate electrode. The gate electrode has a buried portion formed in each of the trenches and a protruding portion situating above the buried portion and having a width larger than that of the buried portion. The introducing the impurity includes introducing an impurity into the semiconductor layer below the protruding portion by oblique ion implantation.
摘要翻译：一种方法（和结果）包括形成具有多个条状沟槽的半导体层，形成部分地埋设在多个沟槽中的每一个中的栅电极，并且在形成栅电极之后通过离子注入将杂质引入半导体层。栅电极具有形成在每个沟槽中的掩埋部分和位于掩埋部分上方并且具有大于掩埋部分的宽度的突出部分。引入杂质包括通过倾斜离子注入将杂质引入到突出部分下方的半导体层中。

6. 发明授权

US07704827B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07704827B2
公开(公告)日：2010-04-27
申请号：US11984043
申请日：2007-11-13
申请人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
发明人： Yoshimitsu Murase , Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko
IPC分类号： H01L21/8242
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/66734
摘要： An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate trench and a polysilicon is formed in the gate trench with the gate insulator interposed therebetween. An HTO film is formed on the surface of the polysilicon and the n− epitaxial layer. At this time, an ion plantation is performed to the epitaxial layer through the HTO film. Hence, a p diffused base layer, an n+ diffused source layer, an n+ diffused source layer is formed. A CVD oxide film is formed on the HTO film. After a BPSG having flowability is deposited on the CVD oxide film, the BPSG film is planarized with a heat treatment of 900-1100 degree Celsius.
摘要翻译：通过外延生长在n +半导体衬底上形成外延层。栅极沟槽形成在栅极沟槽的表面，使得栅极沟槽的底部到达外延层的中间。栅极绝缘体形成在栅极沟槽的内壁上，并且栅极沟槽中形成多晶硅，栅极绝缘体插入其间。在多晶硅和n外延层的表面上形成HTO膜。此时，通过HTO膜对外延层进行离子种植。因此，形成p扩散基极层，n +扩散源极层，n +扩散源极层。在HTO膜上形成CVD氧化膜。在具有流动性的BPSG沉积在CVD氧化物膜上之后，通过900-1100摄氏度的热处理将BPSG膜平坦化。

7. 发明授权

US07622351B2 Method of manufacturing semiconductor device and semiconductor device 失效
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US07622351B2
公开(公告)日：2009-11-24
申请号：US12348467
申请日：2009-01-05
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/456 , H01L29/66734 , H01L29/7808
摘要： A method of manufacturing a semiconductor device, includes: forming a first and a second trench regions adjacent from each other in a first conductivity type semiconductor base; forming a second conductivity type semiconductor region in the semiconductor base between the first and second trench regions; forming a mask on the second conductivity type semiconductor region, the mask covering a central portion between the first and second trench regions; performing ion implantation of a first conductivity type impurity in the second conductivity type semiconductor region with the mask to form a first conductivity type first region and a first conductivity type second region separated from the first conductivity type first region; and performing heat treatment to diffuse the impurity in the first and second regions and to form a connection region between the first and second regions, connection region being shallower than the first and second regions after the heat treatment.
摘要翻译：一种制造半导体器件的方法包括：在第一导电类型半导体基底中形成彼此相邻的第一和第二沟槽区域; 在所述第一和第二沟槽区域之间的所述半导体基底中形成第二导电类型半导体区域; 在所述第二导电类型半导体区域上形成掩模，所述掩模覆盖所述第一和第二沟槽区域之间的中心部分; 在所述第二导电型半导体区域中用所述掩模进行第一导电型杂质的离子注入，以形成与所述第一导电类型的第一区域分离的第一导电类型的第一区域和第一导电类型的第二区域; 并且进行热处理以扩散第一和第二区域中的杂质，并且在第一和第二区域之间形成连接区域，连接区域比热处理后的第一和第二区域浅。

8. 发明授权

US07508030B2 Semiconductor device with vertical MOSFET and method of manufacturing the same 有权
标题翻译：具有垂直MOSFET的半导体器件及其制造方法
公开(公告)号：US07508030B2
公开(公告)日：2009-03-24
申请号：US11265119
申请日：2005-11-03
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42372 , H01L29/4238 , H01L29/66734 , H01L29/7808 , H01L29/7811
摘要： A semiconductor device includes a base region formed above a semiconductor substrate, a source region formed above the base region, a gate electrode filled inside a trench formed above the semiconductor substrate, an interlayer insulation film formed all over the semiconductor substrate, a first contact hole formed in the interlayer insulation film to expose the gate electrode, a second contact hole formed in the interlayer insulation film and the source region to expose the base region, and a conductive film formed above a trench where the first contact hole is formed.
摘要翻译：半导体器件包括形成在半导体衬底上的基极区域，形成在基极区域上方的源极区域，填充在半导体衬底之上形成的沟槽内部的栅极电极，形成在半导体衬底上的层间绝缘膜，第一接触孔形成在所述层间绝缘膜中以暴露所述栅电极，形成在所述层间绝缘膜中的第二接触孔和所述源极区以露出所述基极区;以及导电膜，形成在形成有所述第一接触孔的沟槽之上。

9. 发明申请

US20080265314A1 Semiconductor device having vertical MOSFET and method of manufacturing the same 有权
标题翻译：具有垂直MOSFET的半导体器件及其制造方法
公开(公告)号：US20080265314A1
公开(公告)日：2008-10-30
申请号：US12081931
申请日：2008-04-23
申请人： Kenya Kobayashi
发明人： Kenya Kobayashi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L29/0615 , H01L29/0638 , H01L29/0653 , H01L29/402 , H01L29/41766 , H01L29/4238 , H01L29/456 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L2224/0401 , H01L2224/05558 , H01L2224/05572 , H01L2224/0603 , H01L2224/06051 , H01L2224/13021 , H01L2224/131 , H01L2224/1411 , H01L2224/14131 , H01L2224/16 , H01L2924/0002 , H01L2924/04941 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/00014 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： An ON-resistance of a semiconductor device including a vertical MOSFET whose source electrode, gate electrode, and drain electrode are formed on a single surface is reduced. A drift region which is lower in impurity concentration than a drain region is formed over the drain region. A gate trench and a drain contact trench are simultaneously formed in the drift region. A gate insulating film and a gate electrode are formed in the gate trench. A drain electrode is formed in the drain contact trench. A drain contact region which is higher in impurity concentration than the drift region is formed immediately under the drain contact trench.
摘要翻译：包括在单个表面上形成源电极，栅电极和漏电极的垂直MOSFET的半导体器件的导通电阻减小。在漏极区域上形成杂质浓度低于漏极区域的漂移区域。在漂移区域中同时形成栅极沟槽和漏极接触沟槽。栅极绝缘膜和栅电极形成在栅极沟槽中。在漏极接触沟槽中形成漏电极。在漏极接触沟槽的正下方形成杂质浓度高于漂移区域的漏极接触区域。

10. 发明申请

US20080081422A1 Method of manufacturing semiconductor apparatus 失效
标题翻译：半导体装置的制造方法
公开(公告)号：US20080081422A1
公开(公告)日：2008-04-03
申请号：US11905078
申请日：2007-09-27
申请人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
发明人： Kenya Kobayashi , Hideo Yamamoto , Atsushi Kaneko , Yoshimitsu Murase
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/66734
摘要： A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
摘要翻译：一种制造半导体装置的方法包括在半导体层中形成沟槽，在沟槽内部形成栅电极，在沟槽内部的栅电极上形成热氧化膜，在内部的热氧化膜上形成硅酸盐玻璃膜沟槽，在半导体层内部形成体区，并且在身体区域上形成源区。该方法提供了具有减小的通道长度波动和低导通电阻的半导体装置。

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