专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5438018A Method of making semiconductor device by selective epitaxial growth 失效
标题翻译：通过选择性外延生长制造半导体器件的方法
公开(公告)号：US5438018A
公开(公告)日：1995-08-01
申请号：US162703
申请日：1993-12-07
申请人： Toshihiko Mori , Yoshiki Sakuma
发明人： Toshihiko Mori , Yoshiki Sakuma
IPC分类号： H01L29/205 , H01L21/20 , H01L21/331 , H01L21/822 , H01L21/8252 , H01L27/06 , H01L27/10 , H01L29/68 , H01L29/73
CPC分类号： H01L21/02392 , H01L21/02395 , H01L21/02458 , H01L21/02463 , H01L21/02546 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/8252
摘要： A selective growth mask having a plurality of openings is formed on a semiconductor substrate. Desired epitaxially grown regions are formed on the openings by controlling the upward epitaxial growth from the openings. Two resonance tunnel barrier diodes are formed on respective separated two epitaxially grown regions and connected together. Thereafter, a tunnel barrier diode is formed on the connected two resonance tunnel barrier diodes to form a composite element having an SRAM function. A number of composite functional elements can be integrally formed on a semiconductor substrate by selective growth and a small number of fine processes.
摘要翻译：具有多个开口的选择性生长掩模形成在半导体衬底上。通过从开口控制向外的外延生长，在开口上形成所需的外延生长区域。在分离的两个外延生长区域上形成两个谐振隧道势垒二极管并连接在一起。此后，在连接的两个谐振隧道势垒二极管上形成隧道势垒二极管，以形成具有SRAM功能的复合元件。通过选择性生长和少量精细工艺，可以在半导体衬底上一体形成许多复合功能元件。

2. 发明授权

US5296088A Compound semiconductor crystal growing method 失效
标题翻译：化合物半导体晶体生长方法
公开(公告)号：US5296088A
公开(公告)日：1994-03-22
申请号：US924483
申请日：1992-08-04
申请人： Kunihiko Kodama , Nobuyuki Ohtsuka , Masashi Ozeki , Yoshiki Sakuma
发明人： Kunihiko Kodama , Nobuyuki Ohtsuka , Masashi Ozeki , Yoshiki Sakuma
IPC分类号： C30B25/02 , H01L21/203
CPC分类号： C30B25/02 , C30B29/40 , Y10S148/057
摘要： A compound semiconductor crystal growing method includes the steps of (a) setting a substrate having a substrate surface in a reaction chamber, and (b) supplying a material gas of a compound semiconductor which is to be grown in the form of a crystal on the substrate surface within the reaction chamber and a control gas to the reaction chamber under a predetermined condition, and controlling the supply of the control gas to control an adsorption rate of the material gas on the substrate surface. The control gas makes competitive adsorption with the material gas on the substrate surface but makes no chemical reaction such that no continual accumulation on the substrate surface occurs under the predetermined condition. The competitive adsorption is defined as a phenomenon in which the material gas and the control gas compete and become adsorped on the substrate surface.
摘要翻译：化合物半导体晶体生长方法包括以下步骤：（a）在反应室中设置具有基板表面的基板，（b）将待生长在晶体形式的化合物半导体的材料气体反应室内的基板表面和在预定条件下到达反应室的控制气体，并且控制控制气体的供应以控制材料气体在基板表面上的吸附速率。控制气体与衬底表面上的材料气体进行竞争性吸附，但不发生化学反应，使得在预定条件下不会在衬底表面上发生持续的积累。竞争性吸附被定义为材料气体和对照气体在衬底表面上竞争并被吸附的现象。

3. 发明授权

US5656821A Quantum semiconductor device with triangular etch pit 失效
标题翻译：具有三角蚀刻坑的量子半导体器件
公开(公告)号：US5656821A
公开(公告)日：1997-08-12
申请号：US568124
申请日：1995-12-06
申请人： Yoshiki Sakuma
发明人： Yoshiki Sakuma
IPC分类号： H01L29/12 , H01S5/02 , H01S5/32 , H01S5/34 , H01L29/06 , H01L31/0328 , H01L31/0336
CPC分类号： B82Y20/00 , B82Y10/00 , H01L29/122 , H01L29/125 , H01L29/127 , H01S5/3203 , H01S5/3412 , Y10S438/911
摘要： A semiconductor device is provided, including a semiconductor substrate of zinc blend structure, defined by a principal surface substantially coinciding to a {111}A-oriented crystal surface; an etch pit of the shape of a triangular pyramid, formed on the principal surface of the substrate, the etch pit being defined by side walls merging at an apex of said triangular pyramid, each two of the side walls merging at a valley of the triangular pyramid; and an active part formed on the etch pit; wherein the active part includes a quantum well layer having a first bandgap and provided along the side walls of the etch pit, and a pair of barrier layers having a second, larger bandgap and provided so as to sandwich the quantum well layer. According to the present invention, the quantum semiconductor device includes a quantum box at the apex of the triangular pyramid and quantum wires at the three valleys of the triangular pyramid, in addition to the one-dimensionally confined quantum wells formed by the quantum well layer in correspondence to each of the side walls of the triangular pyramid. By using the quantum box, quantum wires or quantum wells, the device of the present invention can perform various functions.
摘要翻译：提供一种半导体器件，包括由与{111} A取向晶体表面基本一致的主表面限定的锌共混结构的半导体衬底; 形成在基板的主表面上的三角锥形状的蚀刻坑，蚀刻坑由在三角锥的顶点处汇合的侧壁限定，每个两个侧壁在三角形的谷部处合并金字塔; 以及形成在蚀刻坑上的有源部分; 其中所述有源部分包括具有第一带隙并沿着所述蚀刻坑的侧壁设置的量子阱层以及具有第二较大带隙并且被设置为夹着所述量子阱层的一对势垒层。根据本发明，除了由量子阱层形成的一维限制的量子阱之外，量子半导体器件还包括三角锥顶点处的量子箱和三角锥三角的三个量子线对应于三角锥体的每个侧壁。通过使用量子箱，量子线或量子阱，本发明的装置可以执行各种功能。

4. 发明授权

US06777728B2 Semiconductor device and complementary semiconductor device 失效
标题翻译：半导体器件和互补半导体器件
公开(公告)号：US06777728B2
公开(公告)日：2004-08-17
申请号：US10329773
申请日：2002-12-27
申请人： Masashi Shima , Tetsuji Ueno , Yoshiki Sakuma , Shunji Nakamura
发明人： Masashi Shima , Tetsuji Ueno , Yoshiki Sakuma , Shunji Nakamura
IPC分类号： H01L2976
CPC分类号： H01L29/7842 , H01L21/823807 , H01L27/0922 , H01L29/1054 , H01L29/802
摘要： A semiconductor device includes a channel layer, a gate electrode formed on the channel layer, a p-type source region formed on a first side of the channel layer, and a p-type drain region formed on a second side of the channel layer. A heavy-hole band and a light-hole band are separated by compressive strain applied isotropically in an in-plane direction in the channel layer. A channel direction connecting the p-type source and drain regions is set substantially to a direction to maximize hole mobility in the channel layer.
摘要翻译：半导体器件包括沟道层，形成在沟道层上的栅电极，形成在沟道层的第一侧上的p型源极区域和形成在沟道层的第二侧上的p型漏极区域。重孔带和光孔带通过在通道层中的面内方向各向同性地施加的压缩应变来分离。连接p型源极区域和漏极区域的沟道方向基本上设置成使沟道层中的空穴迁移率最大化的方向。

5. 发明授权

US5922621A Quantum semiconductor device and a fabrication process thereof 失效
标题翻译：量子半导体器件及其制造工艺
公开(公告)号：US5922621A
公开(公告)日：1999-07-13
申请号：US832185
申请日：1997-04-08
申请人： Yoshiki Sakuma
发明人： Yoshiki Sakuma
IPC分类号： H01L29/12 , H01S5/02 , H01S5/32 , H01S5/34 , H01L21/302
CPC分类号： B82Y20/00 , B82Y10/00 , H01L29/122 , H01L29/125 , H01L29/127 , H01S5/3203 , H01S5/3412 , Y10S438/911
摘要： A method for fabricating a quantum semiconductor device includes the steps of forming an etch pit of a triangular pyramid on a {111}A-oriented principal surface of a substrate having zinc blende structure by a dry etching process, and depositing semiconductor layers forming a quantum structure consecutively on the etch pit.
摘要翻译：一种制造量子半导体器件的方法包括以下步骤：通过干蚀刻工艺在具有锌闪锌粉结构的基底的{111} A取向主表面上形成三角锥的蚀刻坑，并沉积形成量子的半导体层结构连续地在蚀刻坑上。

6. 发明授权

US6011271A Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6011271A
公开(公告)日：2000-01-04
申请号：US678549
申请日：1996-07-09
申请人： Yoshiki Sakuma , Yoshihiro Sugiyama , Shunichi Muto
发明人： Yoshiki Sakuma , Yoshihiro Sugiyama , Shunichi Muto
IPC分类号： H01L21/20 , H01L21/306 , H01L29/04 , H01L29/12 , H01S5/227 , H01L29/06
CPC分类号： B82Y10/00 , H01L21/02381 , H01L21/02543 , H01L21/02546 , H01L21/0262 , H01L21/02642 , H01L21/30612 , H01L29/045 , H01L29/125 , H01L29/127 , H01S5/227
摘要： In a semiconductor device, concave sections in which an opening area becomes small in proportion as a depth becomes deep are formed in a crystal layer, and a quantum structure is formed on at least one crystal face of a bottom section of the concave section and a border formed between plural sidewalls thereof. In case the quantum structure is formed in the bottom section, a quantum box is formed therein. If the quantum structure is formed in the border between the sidewalls of the concave section, a quantum wire is formed therein. In case the quantum structure is formed in the sidewall of the concave section, a two-dimensional quantum well is formed therein.
摘要翻译：在半导体器件中，在晶体层中形成开口面积变深的比例变小的凹部，在凹部的底部的至少一个晶面上形成量子结构，边界在其多个侧壁之间形成。在底部形成量子结构的情况下，在其中形成量子箱。如果量子结构形成在凹部的侧壁之间的边界上，则在其中形成量子线。在量子结构形成在凹部的侧壁的情况下，形成二维量子阱。

7. 发明授权

US5574308A Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5574308A
公开(公告)日：1996-11-12
申请号：US488057
申请日：1995-06-07
申请人： Toshihiko Mori , Yoshiki Sakuma
发明人： Toshihiko Mori , Yoshiki Sakuma
IPC分类号： H01L29/205 , H01L21/20 , H01L21/331 , H01L21/822 , H01L21/8252 , H01L27/06 , H01L27/10 , H01L29/68 , H01L29/73 , H01L29/06
CPC分类号： H01L21/02392 , H01L21/02395 , H01L21/02458 , H01L21/02463 , H01L21/02546 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/8252
摘要： A selective growth mask having a plurality of openings is formed on a semiconductor substrate. Desired epitaxially grown regions are formed on the openings by controlling the upward epitaxial growth from the openings. Two resonance tunnel barrier diodes are formed on respective separated two epitaxially grown regions and connected together. Thereafter, a tunnel barrier diode is formed on the connected two resonance tunnel barrier diodes to form a composite functional element having an SRAM function. A number of composite functional elements can be integrally formed on a semiconductor substrate by selective growth and a small number of fine processes.
摘要翻译：具有多个开口的选择性生长掩模形成在半导体衬底上。通过从开口控制向外的外延生长，在开口上形成所需的外延生长区域。在分离的两个外延生长区域上形成两个谐振隧道势垒二极管并连接在一起。此后，在连接的两个谐振隧道阻挡二极管上形成隧道势垒二极管，以形成具有SRAM功能的复合功能元件。通过选择性生长和少量精细工艺，可以在半导体衬底上一体形成许多复合功能元件。

8. 发明授权

US5503105A Deposition method for compound semiconductor forming semiconductor device 失效
标题翻译：化合物半导体形成半导体器件的沉积方法
公开(公告)号：US5503105A
公开(公告)日：1996-04-02
申请号：US403957
申请日：1995-03-14
申请人： Yoshiki Sakuma
发明人： Yoshiki Sakuma
IPC分类号： H01L21/205 , H01L21/20 , H01L33/06 , H01L33/30 , H01S3/00 , H01S5/00 , C30B25/14
CPC分类号： H01L21/0262 , H01L21/02392 , H01L21/02461 , H01L21/02491 , H01L21/02543 , H01L21/02546 , Y10T117/102
摘要： A deposition method of a compound semiconductor forming a semiconductor device comprises the steps of; covering the surface of a compound semiconductor containing a V group element with a III group element with a thickness of one or more monolayers; and forming a second compound semiconductor containing a V group element different from said V group element on said III group element while utilizing said III group element as a protective film for preventing the desorption of said V group element.
摘要翻译：形成半导体器件的化合物半导体的沉积方法包括以下步骤：用含有一个或多个单层厚度的III族元素覆盖含有V族元素的化合物半导体的表面; 以及在利用所述III族元素作为防止所述V族元素解吸的保护膜的同时，形成含有与所述III族元素上的所述V族元素不同的V族元素的第二化合物半导体。

9. 发明授权

US5429068A Deposition method for compound semiconductor forming device 失效
标题翻译：化合物半导体形成装置的沉积方法
公开(公告)号：US5429068A
公开(公告)日：1995-07-04
申请号：US137765
申请日：1993-10-19
申请人： Yoshiki Sakuma
发明人： Yoshiki Sakuma
IPC分类号： H01L21/205 , H01L21/20 , H01L33/06 , H01L33/30 , H01S3/00 , H01S5/00 , C30B25/16
CPC分类号： H01L21/0262 , H01L21/02392 , H01L21/02461 , H01L21/02491 , H01L21/02543 , H01L21/02546 , Y10T117/102
摘要： A deposition method of a compound semiconductor forming a semiconductor device comprises the steps of; covering the surface of a compound semiconductor containing a V group element with a III group element with a thickness of one or more monolayers; and forming a second compound semiconductor containing a V group element different from said V group element on said III group element while utilizing said III group element as a protective film for preventing the desorption of said V group element.
摘要翻译：形成半导体器件的化合物半导体的沉积方法包括以下步骤：用含有一个或多个单层厚度的III族元素覆盖含有V族元素的化合物半导体的表面; 以及在利用所述III族元素作为防止所述V族元素解吸的保护膜的同时，形成含有与所述III族元素上的所述V族元素不同的V族元素的第二化合物半导体。

10. 发明授权

US06459107B2 Photodetector having a mixed crystal layer of SiGeC 有权
标题翻译：具有SiGeC的混晶层的光电检测器
公开(公告)号：US06459107B2
公开(公告)日：2002-10-01
申请号：US09793696
申请日：2001-02-27
申请人： Yoshihiro Sugiyama , Yoshiki Sakuma
发明人： Yoshihiro Sugiyama , Yoshiki Sakuma
IPC分类号： H01L148
CPC分类号： H01L31/0312 , H01L31/02005 , H01L31/03125 , H01L31/1075
摘要： A photodetector includes a substrate and an optical absorption layer provided on the substrate, wherein the optical absorption layer is formed of a mixed crystal of Si, Ge and C.
摘要翻译：光电检测器包括基板和设置在基板上的光吸收层，其中光吸收层由Si，Ge和C的混合晶体形成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式