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1. 发明授权

US4656417A Test circuit for differential cascode voltage switch 失效
标题翻译：差分共源共栅电压开关测试电路
公开(公告)号：US4656417A
公开(公告)日：1987-04-07
申请号：US759804
申请日：1985-07-29
申请人： Edward S. Kirkpatrick , Eric P. Kronstadt , Robert K. Montoye , Winfried W. Wilcke
发明人： Edward S. Kirkpatrick , Eric P. Kronstadt , Robert K. Montoye , Winfried W. Wilcke
IPC分类号： H03K17/00 , G01R31/28 , G01R31/3185 , G06F11/00 , G06F11/267
CPC分类号： G06F11/2215 , G01R31/318541 , G01R31/318572 , G01R31/31858 , G06F11/0751
摘要： An improved testing and checking circuit for a Differential Cascode Voltage Switch which uses N-devices for both the invalid (0,0) and (1,1) state detection of Q and Q switch signals, and uses decoupling pass devices for sampling the data at the fall of the system C-clock, additionally allowing simultaneous pre-charging and error detection. The testing and checking circuit is incorporated in a hierarchical scheme, which uses the system C-clock for input to the latches, decoupling of the buffers, and pulling up and down the error lines. The error fault is held in a system latch. Also described is a circuit scheme which self tests a large macro using only the C-clock and latches the result in a single latch. More particularly, the described circuit employs the Q and Q signals in a NOR configuration, thus detecting if neither signal has sufficient voltage to pull down the load device which consists of a P-device whose gate is attached to the C-clock. The resulting signal is run to a gate in parallel with the two N-devices. Thus, the two low signals allow this NOR gate to rise and produce a pulldown leg to an error line. An invalid signal condition is detected if either both signals are sufficiently high to turn on an N-device or neither signal is high enough to turn on an N-device. Therefore, the described circuit registers a failure if and only if there is the potential for a tree with the same inputs to enter an invalid state.
摘要翻译：用于差分串联电压开关的改进的测试和检查电路，其使用N个器件用于Q和＆amp; upbar＆Q开关信号的无效（0,0）和（1,1）状态检测，并使用去耦通设备进行采样数据在系统C-clock掉落时，另外允许同时进行预充电和错误检测。测试和检查电路并入分层方案，其使用系统C时钟输入到锁存器，解耦缓冲器以及上下错误线。错误故障保存在系统锁存器中。还描述了一种电路方案，其仅使用C时钟自检测大宏，并将结果锁存在单个锁存器中。更具体地，所描述的电路采用NOR配置中的Q和＆amp; Upbar＆Q信号，从而检测两个信号是否没有足够的电压来下拉由栅极连接到C时钟的P装置构成的负载装置。结果信号与两个N器件并行运行到门。因此，两个低信号允许该或非门上升并产生到故障线的下拉腿。如果两个信号都足够高以接通N装置，或者两个信号都不足够高以打开N装置，则检测到无效信号条件。因此，当且仅当存在具有相同输入的树进入无效状态的可能性时，所描述的电路注册失败。

2. 发明授权

US4713773A Method for distributing wire load in a multilayer package and the resulting product 失效
标题翻译：在多层封装中分配电线负载的方法以及所得产品
公开(公告)号：US4713773A
公开(公告)日：1987-12-15
申请号：US639570
申请日：1984-08-10
申请人： John F. Cooper , Edward S. Kirkpatrick , Ralph Linsker
发明人： John F. Cooper , Edward S. Kirkpatrick , Ralph Linsker
IPC分类号： G06F1/18 , G06F17/11 , G06F17/50 , G06F19/00 , H05K3/00 , G06F15/32 , G06F7/00
CPC分类号： G06F17/5077 , H05K3/0005
摘要： A method for distributing wire load among the layers of a multilayer interconnection package such that in each region of the package, the wire load is balanced among all layers and such that specified subsets of two-pin connections may be constrained to lie within the same layer.
摘要翻译：一种用于在多层互连封装的层之间分配电线负载的方法，使得在封装的每个区域中，电线负载在所有层之间平衡，并且使得两引脚连接的指定子集可以被限制在同一层内。

3. 发明授权

US4495559A Optimization of an organization of many discrete elements 失效
标题翻译：优化多个离散元素的组织
公开(公告)号：US4495559A
公开(公告)日：1985-01-22
申请号：US317651
申请日：1981-11-02
申请人： Charles D. Gelatt, Jr. , Edward S. Kirkpatrick
发明人： Charles D. Gelatt, Jr. , Edward S. Kirkpatrick
IPC分类号： H01L21/822 , G06F17/50 , H01L21/82 , H01L27/04 , G06F15/46
CPC分类号： G06F17/5072
摘要： The overall arrangement of a large number of discrete objects may be optimized with relation to the function of or the space occupied by the arrangement by establishing a suitability measure, or score, for each configuration of the arrangement, in relation to the function of or volume occupied, generating random local changes in the arrangement, scoring the effect of the individual changes and subjecting all objects in the arrangement to a random series of incremental changes whose outcome is on average predictable. The procedure lends itself to computer simulation. It may be applied to sequencing and scheduling problems, bin packing types of problems and in complex design problems such as semiconductor chip placement, wiring network routing and logic partitioning.
摘要翻译：可以通过针对布置的每个配置建立适合性度量或得分来相对于功能或体积的功能来优化大量离散对象的整体布置，该功能或该布置占据的空间占用，在安排中产生随机的局部变化，评估个体变化的影响，并使排列中的所有对象随机一系列增量变化，其结果平均可预测。该程序适用于计算机模拟。它可能适用于排序和调度问题，bin包装类型的问题和复杂的设计问题，如半导体芯片布局，布线网络路由和逻辑分区。

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