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1. 发明授权

US06566249B1 Planarized semiconductor interconnect topography and method for polishing a metal layer to form wide interconnect structures 有权
公开(公告)号：US06566249B1
公开(公告)日：2003-05-20
申请号：US09189411
申请日：1998-11-09
申请人： William W. C. Koutny, Jr. , Anantha R. Sethuraman , Christopher A. Seams
发明人： William W. C. Koutny, Jr. , Anantha R. Sethuraman , Christopher A. Seams
IPC分类号： H01L214763
CPC分类号： H01L21/7684
摘要： The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by selectively etching a dielectric layer to form a plurality of posts surrounded by trenches. The trenches are filled with a conductive material, such as a metal, deposited to a level spaced above the upper surfaces of the dielectric layer and the posts. The surface of the conductive material is then polished to a level substantially coplanar with the upper surfaces of the dielectric layer and the posts. Advantageously, the polish rate of the conductive material above the trenches is substantially uniform. In this manner, the topological surface of the resulting interconnect level is substantially void of surface disparity.

2. 发明授权

US06361415B1 Employing an acidic liquid and an abrasive surface to polish a semiconductor topography 有权
标题翻译：使用酸性液体和研磨表面来抛光半导体形貌
公开(公告)号：US06361415B1
公开(公告)日：2002-03-26
申请号：US09764590
申请日：2001-01-17
申请人： Anantha R. Sethuraman , William W. C. Koutny, Jr.
发明人： Anantha R. Sethuraman , William W. C. Koutny, Jr.
IPC分类号： B24B719
CPC分类号： H01L21/31053
摘要： The present invention advantageously provides a method and apparatus for polishing a semiconductor topography by applying a liquid which is void of particles between the topography and an abrasive polishing pad surface. The semiconductor topography is rotated relative to the polishing surface to polish elevationally raised regions of the topography. The particles are fixed within the polishing surface which may comprise a polymeric material. In one embodiment, the liquid may comprise water diluted with acid. If the liquid is adjusted to have a pH between 6.0 and 7.0, the polishing process may be used to remove a silicon dioxide layer from the topography at a faster rate than a silicon nitride layer residing beneath the oxide layer. Alternately, a metal may be selectively removed from above an oxide layer if the polishing liquid has a pH between 2.0 and 5.0. In another embodiment, the liquid may be deionized water. The water does not react with the material being polished. The polishing pad is made of a non-deformable material, and thus does not conform to the elevationally disparate semiconductor topography. Therefore, elevationally raised regions of the topography are removed at a faster rate than elevationally recessed regions.
摘要翻译：本发明有利地提供了一种通过在地形和研磨抛光垫表面之间施加无颗粒的液体来研磨半导体形貌的方法和装置。半导体形貌相对于抛光表面旋转以抛光地形的高度升高的区域。颗粒固定在抛光表面内，其可以包括聚合物材料。在一个实施方案中，液体可以包含用酸稀释的水。如果将液体调节至pH在6.0和7.0之间，则抛光过程可以以比位于氧化物层下方的氮化硅层更快的速度从形貌去除二氧化硅层。或者，如果研磨液的pH在2.0和5.0之间，则可以从氧化物层上方选择性地除去金属。在另一个实施方案中，液体可以是去离子水。水不与正在抛光的材料反应。抛光垫由不可变形材料制成，因此不符合高度不同的半导体形貌。因此，地形垂直升高的区域以比垂直凹陷区域更快的速度被去除。

3. 发明授权

US6143663A Employing deionized water and an abrasive surface to polish a semiconductor topography 失效
标题翻译：使用去离子水和磨料表面抛光半导体形貌
公开(公告)号：US6143663A
公开(公告)日：2000-11-07
申请号：US12089
申请日：1998-01-22
申请人： William W. C. Koutny, Jr.
发明人： William W. C. Koutny, Jr.
IPC分类号： H01L21/3105 , H01L21/321 , H01L21/302
CPC分类号： H01L21/3212 , H01L21/31055
摘要： The present invention advantageously provides a method and apparatus for polishing a semiconductor topography by applying a liquid which is void of particles between the topography and an abrasive polishing pad surface. The semiconductor topography is rotated relative to the polishing surface to polish elevationally raised regions of the topography. The particles are fixed within the polishing surface which may comprise a polymeric material. In one embodiment, the liquid may comprise water diluted with acid. If the liquid is adjusted to have a pH between 6.0 and 7.0, the polishing process may be used to remove a silicon dioxide layer from the topography at a faster rate than a silicon nitride layer residing beneath the oxide layer. Alternately, a metal may be selectively removed from above an oxide layer if the polishing liquid has a pH between 2.0 and 5.0. In another embodiment, the liquid may be deionized water. The water does not react with the material being polished. The polishing pad is made of a non-deformable material, and thus does not conform to the elevationally disparate semiconductor topography. Therefore, elevationally raised regions of the topography are removed at a faster rate than elevationally recessed regions.
摘要翻译：本发明有利地提供了一种通过在地形和研磨抛光垫表面之间施加无颗粒的液体来研磨半导体形貌的方法和装置。半导体形貌相对于抛光表面旋转以抛光地形的高度升高的区域。颗粒固定在抛光表面内，其可以包括聚合物材料。在一个实施方案中，液体可以包含用酸稀释的水。如果将液体调节至pH在6.0和7.0之间，则抛光过程可以以比位于氧化物层下方的氮化硅层更快的速度从形貌去除二氧化硅层。或者，如果研磨液的pH在2.0和5.0之间，则可以从氧化物层上方选择性地除去金属。在另一个实施方案中，液体可以是去离子水。水不与正在抛光的材料反应。抛光垫由不可变形材料制成，因此不符合高度不同的半导体形貌。因此，地形垂直升高的区域以比垂直凹陷区域更快的速度被去除。

4. 发明授权

US06969684B1 Method of making a planarized semiconductor structure 有权
标题翻译：制造平面化半导体结构的方法
公开(公告)号：US06969684B1
公开(公告)日：2005-11-29
申请号：US09846119
申请日：2001-04-30
申请人： Yitzhak Gilboa , William W. C. Koutny, Jr. , Steven Hedayati , Krishnaswamy Ramkumar
发明人： Yitzhak Gilboa , William W. C. Koutny, Jr. , Steven Hedayati , Krishnaswamy Ramkumar
IPC分类号： H01L21/302 , H01L21/3105 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/31053 , H01L21/31055
摘要： A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not include a polish stop material. Preferably, the upper surface of the topography formed by polishing is spaced sufficiently above the underlying layer to avoid polishing the underlying layer. The entirety of the upper surface may be simultaneously etched to expose the underlying layer. In an embodiment, the underlying layer may comprise a lateral variation in polish characteristics. The method may include using fixed abrasive polishing of a dielectric layer for reducing a required thickness of an additional layer underlying the dielectric layer. Such a method may be useful when exposing an underlying layer is desirable by techniques other than polishing.
摘要翻译：提供了一种从抛光过程中消除抛光停止层的方法。特别地，提供了一种方法，其可以包括抛光半导体形貌的上层以形成在下层之上的高度上的上表面，其中上表面不包括抛光停止材料。优选地，通过抛光形成的形貌的上表面被充分地间隔在下面的层上，以避免抛光下面的层。可以同时蚀刻整个上表面以暴露下层。在一个实施例中，下层可以包括抛光特性的横向变化。该方法可以包括使用介电层的固定研磨抛光来减少介电层下面的附加层的所需厚度。当通过除了抛光之外的技术来期望暴露下层时，这种方法可能是有用的。

5. 发明授权

US06171180B2 Planarizing a trench dielectric having an upper surface within a trench spaced below an adjacent polish stop surface 失效
标题翻译：平面化沟槽电介质，其具有在相邻抛光停止表面之下间隔开的沟槽内的上表面
公开(公告)号：US06171180B2
公开(公告)日：2001-01-09
申请号：US09052219
申请日：1998-03-31
申请人： William W. C. Koutny, Jr. , Chidambaram G. Kallingal , Krishnaswamy Ramkumar
发明人： William W. C. Koutny, Jr. , Chidambaram G. Kallingal , Krishnaswamy Ramkumar
IPC分类号： B24B2900
CPC分类号： H01L21/31053 , H01L21/76224
摘要： The present invention advantageously provides a method for using an abrasive surface and a particle-free liquid to polish a dielectric, wherein the dielectric is deposited within an isolation trench and across a polish stop surface such that a recess region of the dielectric is spaced below the polish stop surface. In an embodiment, the dielectric is an isolation oxide, and the polish stop surface belongs to an upper surface of a nitride layer formed above a silicon-based substrate. The surface of the dielectric is positioned laterally adjacent the abrasive polishing surface such that the particle-free liquid is positioned at the interface between the dielectric and the polishing surface. The particle-free liquid is preferably deionized water, and the abrasive polishing surface is preferably a polymeric matrix entrained with particles composed of, e.g., ceria. A force configured perpendicular to the backside of the substrate is applied to the polishing surface to force the dielectric surface against the polishing surface while the polishing surface is being rotated relative to the dielectric. As a result, elevationally raised regions of the dielectric are polished to the recessed region of the dielectric, planarizing the dielectric surface. The polish rate of the dielectric is substantially greater than that of the polish stop surface, and thus the polishing stop layer remains intact above the substrate. The polish rate of the elevationally raised regions of the dielectric is also greater than that of the recess region of the dielectric.
摘要翻译：本发明有利地提供了一种使用研磨表面和无颗粒的液体来抛光电介质的方法，其中电介质沉积在隔离沟槽内并穿过抛光止动表面，使得电介质的凹陷区域间隔开抛光停止表面。在一个实施例中，电介质是隔离氧化物，并且抛光停止表面属于在硅基衬底上形成的氮化物层的上表面。电介质的表面位于研磨抛光表面的横向附近，使得无颗粒的液体位于电介质和抛光表面之间的界面处。无颗粒液体优选为去离子水，研磨抛光表面优选为与例如二氧化铈组成的颗粒夹带的聚合物基质。垂直于衬底背面的力被施加到抛光表面，以在抛光表面相对于电介质旋转时迫使电介质表面抵靠抛光表面。结果，电介质的垂直升高的区域被抛光到电介质的凹陷区域，使电介质表面平坦化。电介质的抛光速率基本上大于抛光止动表面的抛光速率，因此抛光停止层在基材上方保持完整。电介质的高度升高区域的抛光速率也大于电介质凹槽区域的抛光速率。

6. 发明授权

US06740588B1 Smooth metal semiconductor surface and method for making the same 有权
标题翻译：平滑的金属半导体表面及其制造方法
公开(公告)号：US06740588B1
公开(公告)日：2004-05-25
申请号：US10113309
申请日：2002-03-29
申请人： William W. C. Koutny, Jr.
发明人： William W. C. Koutny, Jr.
IPC分类号： H01L21302
CPC分类号： H01L27/222 , H01L21/3212 , H01L21/7684
摘要： A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the metal layer may be substantially absent of any material laterally adjacent to the metal layer during polishing. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained. As such, the method may include reducing the mean surface roughness of a metal layer. For example, the method may include reducing the mean surface roughness of a metal layer by at least a factor of ten.
摘要翻译：提供了一种降低金属层的表面粗糙度的方法。在一些实施例中，该方法可以包括将金属层抛光到基本上高于金属层正下方布置的任何层的水平。在一些情况下，包括金属层的半导体形貌可以在抛光期间基本上不存在与金属层横向相邻的任何材料。在任一情况下，可以获得具有平均表面粗糙度小于在金属层沉积期间获得的平均表面粗糙度的金属层的半导体形貌。因此，该方法可以包括降低金属层的平均表面粗糙度。例如，该方法可以包括将金属层的平均表面粗糙度降低至少十倍。

7. 发明授权

US08093128B2 Integration of non-volatile charge trap memory devices and logic CMOS devices 有权
公开(公告)号：US08093128B2
公开(公告)日：2012-01-10
申请号：US12125864
申请日：2008-05-22
申请人： William W. C. Koutny, Jr. , Sam Geha , Igor Kouznetsov , Krishnaswamy Ramkumar , Fredrick B. Jenne , Sagy Levy , Ravindra Kapre , Jeremy Warren
发明人： William W. C. Koutny, Jr. , Sam Geha , Igor Kouznetsov , Krishnaswamy Ramkumar , Fredrick B. Jenne , Sagy Levy , Ravindra Kapre , Jeremy Warren
IPC分类号： H01L29/792
CPC分类号： H01L29/7833 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7836 , H01L29/7843
摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

8. 发明授权

US07329934B1 Smooth metal semiconductor surface and method for making the same 有权
标题翻译：平滑的金属半导体表面及其制造方法
公开(公告)号：US07329934B1
公开(公告)日：2008-02-12
申请号：US10850247
申请日：2004-05-20
申请人： William W. C. Koutny, Jr.
发明人： William W. C. Koutny, Jr.
IPC分类号： H01L21/82
CPC分类号： H01L27/222 , H01L21/3212 , H01L21/7684
摘要： A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the metal layer may be substantially absent of any material laterally adjacent to the metal layer during polishing. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained. As such, the method may include reducing the mean surface roughness of a metal layer. For example, the method may include reducing the mean surface roughness of a metal layer by at least a factor of ten.
摘要翻译：提供了一种降低金属层的表面粗糙度的方法。在一些实施例中，该方法可以包括将金属层抛光到基本上高于金属层正下方布置的任何层的水平。在一些情况下，包括金属层的半导体形貌可以在抛光期间基本上不存在与金属层横向相邻的任何材料。在任一情况下，可以获得具有平均表面粗糙度小于在金属层沉积期间获得的平均表面粗糙度的金属层的半导体形貌。因此，该方法可以包括降低金属层的平均表面粗糙度。例如，该方法可以包括将金属层的平均表面粗糙度降低至少十倍。

9. 发明授权

US06828678B1 Semiconductor topography with a fill material arranged within a plurality of valleys associated with the surface roughness of the metal layer 有权
标题翻译：半导体形貌与填充材料排列在与金属层的表面粗糙度相关联的多个谷内
公开(公告)号：US06828678B1
公开(公告)日：2004-12-07
申请号：US10112833
申请日：2002-03-29
申请人： William W. C. Koutny, Jr.
发明人： William W. C. Koutny, Jr.
IPC分类号： H01L2352
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/32139 , H01L21/76834 , H01L21/76837 , H01L23/522 , H01L43/08 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include depositing a fill layer upon a metal layer and subsequently polishing the fill layer. In some cases, the method may form a surface in which an upper surface of the fill layer is substantially level with at least one of the peaks associated with the surface roughness of the metal layer. In some cases, the surface may include portions of the metal layer and portions of the fill layer residing above the metal layer. In other cases, the method may include forming a surface in which the fill layer is arranged above the metal layer-fill layer interface. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained.
摘要翻译：提供了一种降低金属层的表面粗糙度的方法。在一些实施例中，该方法可以包括将填充层沉积在金属层上并随后抛光填充层。在一些情况下，该方法可以形成其中填充层的上表面与至少一个与金属层的表面粗糙度相关联的峰基本上水平的表面。在一些情况下，表面可以包括金属层的部分和位于金属层上方的填充层的部分。在其他情况下，该方法可以包括形成其中填充层布置在金属层 - 填充层界面之上的表面。在任一情况下，可以获得具有平均表面粗糙度小于在金属层沉积期间获得的平均表面粗糙度的金属层的半导体形貌。

10. 发明授权

US06302766B1 System for cleaning a surface of a dielectric material 有权
标题翻译：用于清洁电介质材料表面的系统
公开(公告)号：US06302766B1
公开(公告)日：2001-10-16
申请号：US09394819
申请日：1999-09-13
申请人： Anantha R. Sethuraman , William W. C. Koutny, Jr.
发明人： Anantha R. Sethuraman , William W. C. Koutny, Jr.
IPC分类号： B24B100
CPC分类号： H01L21/31053 , B24B37/107 , C09K13/04 , H01L21/02065 , H01L21/6704 , H01L21/67051 , H01L21/67057
摘要： The present invention provides a method for cleaning particles from a semiconductor topography that has been polished using a fixed-abrasive polishing process by applying a cleaning solution including either (a) an acid and a peroxide or (b) an acid oxidant to the topography. According to an embodiment, a semiconductor topography is polished by a fixed-abrasive process in which the topography is pressed face-down on a rotating polishing pad having particles embedded in the pad while a liquid absent of particulate matter is dispensed onto the pad. The particles may include, e.g., cerium oxide, cerium dioxide, &agr;alumina, &ggr;alumina, silicon dioxide, titanium oxide, chromium oxide, or zirconium oxide. A cleaning solution comprising either (a) an acid and a peroxide, e.g., hydrogen peroxide, or (b) an acid oxidant is applied to the semiconductor topography after the polishing process is completed. Examples of acids that may be used include, but are not limited to, sulfuric acid, hydrochloric acid, hydrobromic acid, hydrofluoric acid, formic acid, acetic acid, nitric acid, perchloric acid, perbromic acid, performic acid, phosphoric acid, and peracetic acid Advantageously, the cleaning solution effectively eliminates all or at least a significant portion of the particles on the semiconductor topography.
摘要翻译：本发明提供了一种通过将（a）酸和过氧化物或（b）酸性氧化剂）的清洁溶液涂布到地形上，使用固定研磨抛光工艺抛光的半导体形貌的颗粒的清洁方法。根据一个实施例，通过固定研磨工艺抛光半导体形貌，其中将形状面向下压在具有嵌入在衬垫中的颗粒的旋转抛光垫上，而没有颗粒物质的液体被分配到衬垫上。颗粒可以包括例如氧化铈，二氧化铈，α-氧化铝，γ-氧化铝，二氧化硅，氧化钛，氧化铬或氧化锆。在抛光处理完成之后，将包含（a）酸和过氧化物（例如过氧化氢）或（b）酸式氧化剂的清洁溶液施加到半导体形貌。可以使用的酸的实例包括但不限于硫酸，盐酸，氢溴酸，氢氟酸，甲酸，乙酸，硝酸，高氯酸，过溴酸，甲酸，磷酸和过乙酸酸有利地，清洁溶液有效地消除半导体形貌上的所有或至少大部分颗粒。

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