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1. 发明授权

US06969684B1 Method of making a planarized semiconductor structure 有权
标题翻译：制造平面化半导体结构的方法
公开(公告)号：US06969684B1
公开(公告)日：2005-11-29
申请号：US09846119
申请日：2001-04-30
申请人： Yitzhak Gilboa , William W. C. Koutny, Jr. , Steven Hedayati , Krishnaswamy Ramkumar
发明人： Yitzhak Gilboa , William W. C. Koutny, Jr. , Steven Hedayati , Krishnaswamy Ramkumar
IPC分类号： H01L21/302 , H01L21/3105 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/31053 , H01L21/31055
摘要： A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not include a polish stop material. Preferably, the upper surface of the topography formed by polishing is spaced sufficiently above the underlying layer to avoid polishing the underlying layer. The entirety of the upper surface may be simultaneously etched to expose the underlying layer. In an embodiment, the underlying layer may comprise a lateral variation in polish characteristics. The method may include using fixed abrasive polishing of a dielectric layer for reducing a required thickness of an additional layer underlying the dielectric layer. Such a method may be useful when exposing an underlying layer is desirable by techniques other than polishing.
摘要翻译：提供了一种从抛光过程中消除抛光停止层的方法。特别地，提供了一种方法，其可以包括抛光半导体形貌的上层以形成在下层之上的高度上的上表面，其中上表面不包括抛光停止材料。优选地，通过抛光形成的形貌的上表面被充分地间隔在下面的层上，以避免抛光下面的层。可以同时蚀刻整个上表面以暴露下层。在一个实施例中，下层可以包括抛光特性的横向变化。该方法可以包括使用介电层的固定研磨抛光来减少介电层下面的附加层的所需厚度。当通过除了抛光之外的技术来期望暴露下层时，这种方法可能是有用的。

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