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1. 发明授权

US07949981B2 Via density change to improve wafer surface planarity 有权
标题翻译：通过密度变化来提高晶片表面平面度
公开(公告)号：US07949981B2
公开(公告)日：2011-05-24
申请号：US12183313
申请日：2008-07-31
申请人： Stephen E. Greco
发明人： Stephen E. Greco
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Changing a via density for viafill vias to improve wafer surface planarity for later photolithography is provided, in one embodiment, by obtaining a circuit design including a plurality of viafill vias having differing via density across the circuit design, each viafill via interconnecting non-functional metal fill shapes in different layers of the circuit design; selecting a region of the circuit design to evaluate using an evaluation window; determining a via density within the evaluation window; and changing a number of viafill vias within the region in the circuit design in response to the via density being different than a threshold via density that is selected such that a coating deposited over the plurality of vias presents a substantially planar surface.
摘要翻译：在一个实施例中，通过获得包括跨越电路设计的具有不同通孔密度的多个通孔填充通孔的电路设计，提供了用于通孔填充孔的通孔密度以改善用于后续光刻的晶片表面平面度，每个通孔互连非功能性金属填充形状在不同层次的电路设计; 选择电路设计的区域以使用评估窗口进行评估; 确定评估窗口内的通路密度; 以及响应于所述通孔密度不同于选定的阈值通孔密度，使得沉积在所述多个通孔上的涂层呈现基本平坦的表面，在所述电路设计中的所述区域内改变多个通孔填充孔。

2. 发明申请

US20090265673A1 INTERSECT AREA BASED GROUND RULE FOR SEMICONDUCTOR DESIGN 有权
标题翻译：用于半导体设计的基于区域的接地规则
公开(公告)号：US20090265673A1
公开(公告)日：2009-10-22
申请号：US12105299
申请日：2008-04-18
申请人： Albrik Avanessian , Henry A. Bonges, III , Dureseti Chidambarrao , Stephen E. Greco , Douglas W. Kemerer , Tina Wagner
发明人： Albrik Avanessian , Henry A. Bonges, III , Dureseti Chidambarrao , Stephen E. Greco , Douglas W. Kemerer , Tina Wagner
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.
摘要翻译：提供了一种设计规则，其通过估计半导体芯片中的对应结构的物理重叠区域或“交叉区域”来确定两个相邻级别中的两个设计元素之间的重叠程度。物理相交区域的估计可以考虑线边缘偏置，临界尺寸公差，覆盖公差和角舍入，以提供对应于两个设计元素的每个结构的物理面积的精确估计。采用交叉区域作为度量以确定是否符合基本规则，即基于交叉区域来指定接地规则。可以从交叉区域计算其他衍生量，例如电阻，电迁移阻力，预期产量，并且可以有利地用于优化设计数据。

3. 发明授权

US07368302B2 Dynamic metal fill for correcting non-planar region 有权
标题翻译：用于校正非平面区域的动态金属填充
公开(公告)号：US07368302B2
公开(公告)日：2008-05-06
申请号：US10908128
申请日：2005-04-28
申请人： Stephen E. Greco
发明人： Stephen E. Greco
IPC分类号： H01L21/00
CPC分类号： H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Methods and a system are disclosed for correcting a non-planar region during fabrication of a semiconductor product on a wafer. The invention separates an exposure of at least a portion of a fill pattern on a resist from a product exposure so that the fill pattern can be adjusted to correct the non-planar region. In one embodiment, a determination of whether a fill pattern for a metal level above the non-planar region includes a portion over the non-planar region is made. Where a portion of the fill pattern is to be placed over the non-planar region, a pattern factor for exposure of the portion of the fill pattern on a resist is adjusted to correct the non-planar region.
摘要翻译：公开了用于在晶片上制造半导体产品期间校正非平面区域的方法和系统。本发明将抗蚀剂上的填充图案的至少一部分的曝光与产品曝光分开，使得可以调整填充图案以校正非平面区域。在一个实施例中，确定在非平面区域之上的金属水平的填充图案是否包括非平面区域上的部分。在填充图案的一部分被放置在非平面区域上的情况下，调整填充图案的部分在抗蚀剂上的曝光的图案因子以校正非平面区域。

4. 发明授权

US07071099B1 Forming of local and global wiring for semiconductor product 有权
标题翻译：形成半导体产品的本地和全球接线
公开(公告)号：US07071099B1
公开(公告)日：2006-07-04
申请号：US10908623
申请日：2005-05-19
申请人： Stephen E. Greco , Theodorus E. Standaert
发明人： Stephen E. Greco , Theodorus E. Standaert
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76807 , H01L21/76838 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed. In one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit using a dual damascene structure in a first dielectric layer, and BEOL wiring over a second circuit using a single damascene via structure in the first dielectric layer. Then, simultaneously generating BEOL wiring over the first circuit using a dual damascene structure in a second dielectric layer, and BEOL wiring over the second circuit using a single damascene line wire structure in the second dielectric layer. The single damascene via structure has a width approximately twice that of a via portion of the dual damascene structures and the single damascene line wire structure has a width approximately twice that of a line wire portion of the dual damascene structures. A semiconductor product having different width BEOL wiring for different circuits is also disclosed.
摘要翻译：公开了在同一半导体产品即晶片或芯片上形成用于不同电路的不同后端线（BEOL）布线的方法。在一个实施例中，该方法包括使用第一电介质层中的双镶嵌结构在第一电路上同时产生BEOL布线，以及使用第一电介质层中的单镶嵌通孔结构的第二电路上的BEOL布线。然后，使用第二电介质层中的双镶嵌结构同时在第一电路上产生BEOL布线，并且在第二电介质层中使用单个镶嵌线线结构在第二电路上生成BEOL布线。单个镶嵌通孔结构的宽度大约是双镶嵌结构的通孔部分的宽度的两倍，并且单镶嵌线结构的宽度大约是双镶嵌结构的线丝部分的宽度的两倍。还公开了一种用于不同电路的具有不同宽度的BEOL布线的半导体产品。

5. 发明授权

US06221780B1 Dual damascene flowable oxide insulation structure and metallic barrier 失效
标题翻译：双镶嵌可流动氧化物绝缘结构和金属屏障
公开(公告)号：US06221780B1
公开(公告)日：2001-04-24
申请号：US09408351
申请日：1999-09-29
申请人： Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
发明人： Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
IPC分类号： H01L21311
CPC分类号： H01L21/76843 , H01L21/31116 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/7684
摘要： A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.
摘要翻译：一种通过氧化FOX绝缘体的侧壁来保护半导体中的可流动的氧化物绝缘体的方法和结构，可选地将氧化的FOX侧壁氮化，然后覆盖包括侧壁在内的FOX绝缘体中的槽或多个槽的所有表面，导电二级保护层。在多层镶嵌结构中，FOX绝缘体的表面也被氧化，在其上沉积另外的氧化物层，并且沉积在氧化物层上的氮化物层。然后重复步骤以获得可比较的镶嵌结构。材料可以变化，并且每个镶嵌层可以是单镶嵌层或双镶嵌层。

6. 发明授权

US5444015A Larce scale IC personalization method employing air dielectric structure for extended conductors 失效
标题翻译： Larce尺寸IC个性化方法采用空气电介质结构用于扩展导体
公开(公告)号：US5444015A
公开(公告)日：1995-08-22
申请号：US225685
申请日：1994-04-11
申请人： John M. Aitken , Klaus D. Beyer , Billy L. Crowder , Stephen E. Greco
发明人： John M. Aitken , Klaus D. Beyer , Billy L. Crowder , Stephen E. Greco
IPC分类号： H01L27/04 , H01L21/768 , H01L21/822 , H01L23/522 , H01L21/28
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002
摘要： Fabrication methods for forming a network of walls concurrently with the formation of studs for interconnecting plural device layers of a large scale integrated circuit device permits aggressive reduction of the average dielectric constant of air dielectric structures. Wall sections may be positioned to laterally support high aspect ratio connecting studs with a network of open or closed polygons. Wall patterns may also be open from layer to layer to allow formation of large scale air dielectric structures over a plurality of layers in a single material removal step. A wide range of shear strengths and reductions of average dielectric constant can be achieved even within a single device layer of a large scale integrated circuit and exploited to meet circuit design and device fabrication process requirements.
摘要翻译：用于形成用于互连大规模集成电路器件的多个器件层的螺柱的壁的形成网络的制造方法允许大大降低空气电介质结构的平均介电常数。壁部分可以被定位成横向支撑具有开放或闭合多边形网络的高纵横比连接螺柱。壁图案也可以从一层开放，以允许在单个材料去除步骤中在多个层上形成大规模空气介电结构。即使在大规模集成电路的单个器件层内，也可以获得宽范围的剪切强度和平均介电常数的降低，并被用于满足电路设计和器件制造工艺要求。

7. 发明授权

US08492268B2 IC having viabar interconnection and related method 有权
标题翻译： IC具有viabar互连及相关方法
公开(公告)号：US08492268B2
公开(公告)日：2013-07-23
申请号：US13410466
申请日：2012-03-02
申请人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
发明人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
IPC分类号： H01L23/52
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.
摘要翻译：一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar，在第二位置处连接到第一金属层的布线而不是第二金属层的布线。

8. 发明授权

US08484586B2 System and method of predicting problematic areas for lithography in a circuit design 有权
公开(公告)号：US08484586B2
公开(公告)日：2013-07-09
申请号：US13517811
申请日：2012-06-14
申请人： Timothy A. Brunner , Stephen E. Greco , Bernhard R. Liegl , Hua Xiang
发明人： Timothy A. Brunner , Stephen E. Greco , Bernhard R. Liegl , Hua Xiang
IPC分类号： G06F17/50 , G02B7/04 , H01L27/00
CPC分类号： G06F17/5045 , G03F1/144 , G03F1/36 , G03F1/70 , G03F7/705
摘要： A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

9. 发明申请

US20120254812A1 SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN 有权
标题翻译：用于电路设计中的图形的预测问题的系统和方法
公开(公告)号：US20120254812A1
公开(公告)日：2012-10-04
申请号：US13517811
申请日：2012-06-14
申请人： Timothy A. BRUNNER , Stephen E. GRECO , Bernhard R. LIEGL , Hua XIANG
发明人： Timothy A. BRUNNER , Stephen E. GRECO , Bernhard R. LIEGL , Hua XIANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G03F1/144 , G03F1/36 , G03F1/70 , G03F7/705
摘要： A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.
摘要翻译：提供了一种系统和方法，其预测电路设计中的光刻的有问题的区域，更具体地，其使用来自建模工具的建模数据来准确地预测有问题的光刻区域。该方法包括识别模拟晶片的多个瓦片的表面高度，以及数学上模拟光刻工具以确定用于多个瓦片的曝光的最佳焦点平面。

10. 发明申请

US20120164758A1 IC HAVING VIABAR INTERCONNECTION AND RELATED METHOD 有权
标题翻译：具有VIABAR互连的IC和相关方法
公开(公告)号：US20120164758A1
公开(公告)日：2012-06-28
申请号：US13410466
申请日：2012-03-02
申请人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
发明人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
IPC分类号： H01L21/66
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.
摘要翻译：一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar，在第二位置处连接到第一金属层的布线而不是第二金属层的布线。

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