专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5812796A Support structures for an intelligent low power serial bus 失效
标题翻译：支持智能低功率串行总线的结构
公开(公告)号：US5812796A
公开(公告)日：1998-09-22
申请号：US517003
申请日：1995-08-18
申请人： Walter F. Broedner , Anthony M. Fadell
发明人： Walter F. Broedner , Anthony M. Fadell
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/4291
摘要： A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. Each peripheral device includes a plurality of serial bus support structures. For example, the serial bus support structures can include an interrupt generation circuit, a power-on circuit, and a wake-up interrupt generation circuit, and a wake-up interrupt propagation circuit.
摘要翻译：低功耗，单主机，可变时钟速率，菊花链式串行总线将总线调度（主机）连接到一个或多个菊花链外围设备（从站）的链路。总线具有双向串行数据线，双向时钟线，单向中断线，电源线和接地线。每个外围设备包括多个串行总线支持结构。例如，串行总线支持结构可以包括中断产生电路，上电电路和唤醒中断产生电路以及唤醒中断传播电路。

2. 发明授权

US5675811A Method for transmitting information over an intelligent low power serial bus 失效
标题翻译：通过智能低功率串行总线传输信息的方法
公开(公告)号：US5675811A
公开(公告)日：1997-10-07
申请号：US516850
申请日：1995-08-18
申请人： Walter F. Broedner , Anthony M. Fadell , Stephen G. Perlman , John E. Watkins
发明人： Walter F. Broedner , Anthony M. Fadell , Stephen G. Perlman , John E. Watkins
IPC分类号： G06F13/42 , G06F11/30
CPC分类号： G06F13/4291
摘要： A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch in a base station (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. Data and commands are sent from the base station to a peripheral device, and data is received from the peripheral device by the base station by configuring each peripheral device on the bus to receive data and clock signals from the base station in an idle mode of operation. Upon a command send being transmitted by the base station, all peripheral devices on the serial bus between the base station and an addressed peripheral device remain in the idle mode and the addressed peripheral device is connected to the bus so that clock and data signals on the bus to are passed to the peripheral device. When the peripheral devices on the bus are in the idle mode of operation, and the base station transmits a command get to an addressed peripheral device, the addressed peripheral device and all peripheral devices between the addressed peripheral device and the base station are reconfigured to transmit clock and data signals from the addressed peripheral device to the base station.
摘要翻译：低功耗，单主机，可变时钟速率，菊花链式串行总线将基站（主站）中的总线调度连接到一个或多个菊花链外围设备（从站）的链路。总线具有双向串行数据线，双向时钟线，单向中断线，电源线和接地线。数据和命令从基站发送到外围设备，并且基站通过配置总线上的每个外围设备从外围设备接收数据，以在空闲操作模式下从基站接收数据和时钟信号。当基站发送的命令发送时，基站和寻址的外围设备之间的串行总线上的所有外围设备保持在空闲模式，并且所寻址的外围设备连接到总线，使得时钟和数据信号在总线传递到外围设备。当总线上的外围设备处于空闲操作模式时，并且基站向寻址的外围设备发送命令，寻址的外围设备和所寻址的外围设备与基站之间的所有外围设备被重新配置为传送时钟和数据信号从寻址的外围设备到基站。

3. 发明授权

US4631692A RGB interface 失效
标题翻译： RGB接口
公开(公告)号：US4631692A
公开(公告)日：1986-12-23
申请号：US653491
申请日：1984-09-21
申请人： Walter F. Broedner
发明人： Walter F. Broedner
IPC分类号： H04N9/00 , G09G1/28 , G09G5/04 , G09G5/18 , G09G3/02 , H04N1/46
CPC分类号： G09G1/285
摘要： An interface for adapting an Apple.TM. II series computer, having only a video output suitable for driving an NTSC-type monitor to drive an RGB-type monitor. In the preferred embodiment, the interface subdivides the computer's double-density high resolution (HIRES) video mode output having 560 transitions/monitor scan line into any of four (4) video modes for display on the RGB monitor. The interface can be provided on a card incorporated into the computer or as a unit separate and distinct from the computer and connected therewith via a cable.
摘要翻译：用于适应Apple TM II系列计算机的接口，只有一个视频输出适合驱动NTSC型显示器来驱动RGB型显示器。在优选实施例中，该界面将具有560个转换/监视扫描线的计算机的双重密度高分辨率（HIRES）视频模式输出细分为四个（4）视频模式中的任何一个以在RGB监视器上显示。该接口可以设置在结合到计算机中的卡上，或者作为与计算机分离和分离并且经由电缆与之连接的单元。

4. 发明授权

US5938742A Method for configuring an intelligent low power serial bus 失效
标题翻译：配置智能低功率串行总线的方法
公开(公告)号：US5938742A
公开(公告)日：1999-08-17
申请号：US516857
申请日：1995-08-18
申请人： Anthony M. Faddell , Walter F. Broedner
发明人： Anthony M. Faddell , Walter F. Broedner
IPC分类号： G06F13/42 , G06F13/00 , G06F13/14
CPC分类号： G06F13/4256
摘要： A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. A method for configuring the bus includes detecting connection and disconnection of a peripheral device to the bus. In the method, a last peripheral device on the bus is assigned the second status and all other peripheral devices on the bus are assigned the first status. Each peripheral device assigned the first status is configured to pass therethrough an interrupt signal on the bus. The last peripheral device is configured to invert an interrupt signal on the bus from a peripheral device that is newly attached to the bus. A peripheral device newly connected to the bus generates an interrupt signal that is inverted by the last peripheral device and transmitted over the bus to a host computer for the bus. Also, an interrupt signal is driven on the bus by one peripheral device on the bus upon disconnection of another peripheral device on the bus where the another peripheral device is downstream on the bus from the one peripheral device.
摘要翻译：低功耗，单主机，可变时钟速率，菊花链式串行总线将总线调度（主机）连接到一个或多个菊花链外围设备（从站）的链路。总线具有双向串行数据线，双向时钟线，单向中断线，电源线和接地线。用于配置总线的方法包括检测外围设备到总线的连接和断开。在该方法中，总线上的最后一个外围设备被分配第二个状态，总线上的所有其他外围设备被分配第一个状态。分配有第一状态的每个外围设备都配置为通过总线上的中断信号。最后一个外围设备配置为将总线上的中断信号从新连接到总线的外围设备进行反相。新连接到总线的外围设备产生中断信号，该中断信号被最后一个外围设备反相，并通过总线发送到总线的主计算机。此外，总线上的一个外围设备在总线上断开另一个外围设备的总线上的一个外围设备在总线上驱动中断信号，其中另一个外围设备在总线上从一个外围设备下游。

5. 发明授权

US5787298A Bus interface circuit for an intelligent low power serial bus 失效
标题翻译：用于智能低功率串行总线的总线接口电路
公开(公告)号：US5787298A
公开(公告)日：1998-07-28
申请号：US516849
申请日：1995-08-18
申请人： Walter F. Broedner , Anthony M. Faddell
发明人： Walter F. Broedner , Anthony M. Faddell
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/266 , G06F1/26
摘要： A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. Each peripheral device includes a first bidirectional signal line, a second bidirectional signal line coupled to the bus clock and data lines, respectively, and an interface circuit coupled to the first and second bidirectional signal lines. The interface circuit includes a first buffer circuit coupled to the first and second bidirectional signal lines, and a second buffer circuit coupled to the first buffer circuit. A control circuit in the interface circuit couples the first and second buffer circuits where in a first mode of operation, the control circuit passes signals on the first and second bidirectional signal lines through the first and second buffer circuits, and in a second mode of operation, the control circuit passes signals on the first and second bidirectional signal lines through the first buffer circuit and configures the second buffer circuit to terminate the first bidirectional signal line. Thus bus power supply line is coupled to the interface circuit and a voltage on the power supply line is used to power the first and second buffer circuits and the control circuit. The bus interrupt line is coupled to the control circuit of the interface circuit. The interface circuit is also coupled to signal lines of the peripheral device.
摘要翻译：低功耗，单主机，可变时钟速率，菊花链式串行总线将总线调度（主机）连接到一个或多个菊花链外围设备（从站）的链路。总线具有双向串行数据线，双向时钟线，单向中断线，电源线和接地线。每个外围设备分别包括耦合到总线时钟和数据线的第一双向信号线，第二双向信号线和耦合到第一和第二双向信号线的接口电路。接口电路包括耦合到第一和第二双向信号线的第一缓冲电路和耦合到第一缓冲电路的第二缓冲电路。接口电路中的控制电路耦合第一和第二缓冲电路，其中在第一操作模式中，控制电路通过第一和第二缓冲电路通过第一和第二双向信号线上的信号，并且在第二操作模式控制电路通过第一缓冲电路使第一和第二双向信号线上的信号通过，并配置第二缓冲电路以终止第一双向信号线。因此，总线电源线耦合到接口电路，并且使用电源线上的电压为第一和第二缓冲电路和控制电路供电。总线中断线耦合到接口电路的控制电路。接口电路还耦合到外围设备的信号线。

6. 发明授权

US5793993A Method for transmitting bus commands and data over two wires of a serial bus 失效
标题翻译：通过串行总线的两条线传输总线命令和数据的方法
公开(公告)号：US5793993A
公开(公告)日：1998-08-11
申请号：US516840
申请日：1995-08-18
申请人： Walter F. Broedner , Anthony M. Faddell , Stephen G. Perlman , John E. Watkins
发明人： Walter F. Broedner , Anthony M. Faddell , Stephen G. Perlman , John E. Watkins
IPC分类号： G06F13/42 , G06F13/40
CPC分类号： G06F13/4291
摘要： A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. All bus transactions over the bus occur under bus dispatch commands. If a peripheral device interrupts the bus dispatch, bus dispatch issues commands over the bus to determine which device caused the interrupt and what service is being requested by the device. The bus dispatch may then turn control of the data and clock lines over to the peripheral device for a limited amount of time depending on the service requested. New peripheral devices can be connected onto the bus and unused peripheral devices can be disconnected from the bus while the bus is operating without causing a bus failure. Similarly, bus dispatch may enter a low power sleep mode from which it may be awakened by a peripheral device. In some embodiments, additional lines such as battery charging lines and/or signal lines for other serial buses such as RS-232 and RS-422 are provided.
摘要翻译：低功耗，单主机，可变时钟速率，菊花链式串行总线将总线调度（主机）连接到一个或多个菊花链外围设备（从站）的链路。总线具有双向串行数据线，双向时钟线，单向中断线，电源线和接地线。总线上的所有总线事务都发生在总线调度命令下。如果外围设备中断总线调度，总线调度通过总线发出命令，以确定哪个设备导致中断以及设备请求哪些服务。然后，总线调度可以根据所请求的服务将数据和时钟线的控制转移到外围设备一段有限的时间。新的外围设备可以连接到总线上，而总线正在运行时，未使用的外围设备可以与总线断开连接，而不会导致总线故障。类似地，总线调度可以进入低功耗睡眠模式，由此可以由外围设备唤醒。在一些实施例中，提供了用于诸如RS-232和RS-422的其它串行总线的附加线，例如电池充电线和/或信号线。

7. 发明授权

US3950654A Power-on initializing circuit for a calculator system 失效
标题翻译：用于计算机系统的上电初始化电路
公开(公告)号：US3950654A
公开(公告)日：1976-04-13
申请号：US523809
申请日：1974-11-14
申请人： Walter F. Broedner , Ravinder K. Bhatnagar , W. Eugene Hill , Daniel W. Tjoa
发明人： Walter F. Broedner , Ravinder K. Bhatnagar , W. Eugene Hill , Daniel W. Tjoa
IPC分类号： G06F1/24 , H03K3/356 , H03K17/22 , H03K19/017 , H03K19/0944 , H03K1/12 , H03K5/153
CPC分类号： H03K17/223 , G06F1/24 , H03K19/01721 , H03K19/09443 , H03K3/356008 , Y10T307/735
摘要： An initializing circuit for automatically providing a pulse of a duration sufficient to initialize all the relevant storage elements in an electronic calculator computing system having one or two power supplies. It comprises a power-on pulse generator controlled by two phase clock buffers utilizing a feed-back loop including a bit of delay to guarantee a minimum of one bit time duration for the power-on level. The two phase clock buffers are activated at turn-on to remain in a steady state by a power-on level detecting sub-circuit to control the pulse generator. When a one bit pulse is insufficient to initialize the system, a flip-flop and a counter may be used to generate a longer pulse.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式