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1. 发明授权

US3950654A Power-on initializing circuit for a calculator system 失效
标题翻译：用于计算机系统的上电初始化电路
公开(公告)号：US3950654A
公开(公告)日：1976-04-13
申请号：US523809
申请日：1974-11-14
申请人： Walter F. Broedner , Ravinder K. Bhatnagar , W. Eugene Hill , Daniel W. Tjoa
发明人： Walter F. Broedner , Ravinder K. Bhatnagar , W. Eugene Hill , Daniel W. Tjoa
IPC分类号： G06F1/24 , H03K3/356 , H03K17/22 , H03K19/017 , H03K19/0944 , H03K1/12 , H03K5/153
CPC分类号： H03K17/223 , G06F1/24 , H03K19/01721 , H03K19/09443 , H03K3/356008 , Y10T307/735
摘要： An initializing circuit for automatically providing a pulse of a duration sufficient to initialize all the relevant storage elements in an electronic calculator computing system having one or two power supplies. It comprises a power-on pulse generator controlled by two phase clock buffers utilizing a feed-back loop including a bit of delay to guarantee a minimum of one bit time duration for the power-on level. The two phase clock buffers are activated at turn-on to remain in a steady state by a power-on level detecting sub-circuit to control the pulse generator. When a one bit pulse is insufficient to initialize the system, a flip-flop and a counter may be used to generate a longer pulse.

2. 发明授权

US06858450B1 Method of alternating grounded/floating poly lines to monitor shorts 失效
标题翻译：交替接地/浮动多线的方法来监控短路
公开(公告)号：US06858450B1
公开(公告)日：2005-02-22
申请号：US10288871
申请日：2002-11-05
申请人： Samantha L. Doan , Amy C. Tu , W. Eugene Hill
发明人： Samantha L. Doan , Amy C. Tu , W. Eugene Hill
IPC分类号： G11C29/02 , H01L31/26 , H01L21/66
CPC分类号： G11C29/025 , G11C16/04 , G11C29/02 , G11C2029/0403 , G11C2029/5002
摘要： A method for in-line testing of a chip to include multiple independent bit Flash memory devices, includes the steps of: grounding every other polysilicon line on the chip to emulate the multiple independent bit Flash memory devices, where an oxide line reside between every two polysilicon lines; scanning the polysilicon lines with an electron beam; examining voltage contrasts between the polysilicon lines; and determining if there are consecutively grounded polysilicon lines based on the voltage contrasts. If consecutive polysilicon lines appear to be grounded, then this indicates that a bridge defect exists between two of the consecutively grounded polysilicon lines. With this method, bridge defects in multiple independent bit Flash memory devices are better detected, leading to improved yield and reliability of the devices.
摘要翻译：一种用于在线测试芯片以包括多个独立位闪存器件的方法包括以下步骤：将芯片上的每隔一个多晶硅线接地，以模拟多个独立的位闪存器件，其中氧化物线驻留在每两个多晶硅线用电子束扫描多晶硅线; 检查多晶硅线之间的电压对比度; 以及基于电压对比确定是否存在连续接地的多晶硅线。如果连续的多晶硅线看起来接地，则这表明在两个连续接地的多晶硅线之间存在桥缺陷。通过这种方法，可以更好地检测多个独立位闪存器件中的桥接缺陷，从而提高器件的产量和可靠性。

3. 发明授权

US06777708B1 Apparatus and methods for determining floating body effects in SOI devices 失效
标题翻译：用于确定SOI器件中的浮体效应的装置和方法
公开(公告)号：US06777708B1
公开(公告)日：2004-08-17
申请号：US10342541
申请日：2003-01-15
申请人： Hung-Jen Lin , W. Eugene Hill
发明人： Hung-Jen Lin , W. Eugene Hill
IPC分类号： H01L2358
CPC分类号： H01L22/34 , G01R31/2882 , G01R31/3016
摘要： Methods and systems are described for determining floating body delay effects in an SOI wafer, wherein test apparatus is provided in a wafer comprising a plurality of floating body devices fabricated in series in the wafer, and a pulse generation circuit providing a pulse output corresponding to a delay time associated with the floating body chain according to an input pulse edge and a propagated pulse edge from the floating body devices.
摘要翻译：描述了用于确定SOI晶片中的浮体延迟效应的方法和系统，其中测试装置设置在包括在晶片中串联制造的多个浮体装置的晶片中，以及脉冲产生电路，其提供对应于根据输入脉冲边缘和浮体装置的传播脉冲边缘与浮体链相关联的延迟时间。

4. 发明授权

US07032193B1 Differentially mis-aligned contacts in flash arrays to calibrate failure modes 失效
标题翻译：闪存阵列中的差分错误对齐触点，以校准故障模式
公开(公告)号：US07032193B1
公开(公告)日：2006-04-18
申请号：US10320910
申请日：2002-12-17
申请人： W. Eugene Hill
发明人： W. Eugene Hill
IPC分类号： G06F17/50
CPC分类号： H01L27/115 , G11C29/02 , G11C2029/0403 , G11C2029/5002 , H01L21/76816 , H01L27/105 , H01L27/1052 , H01L27/11521
摘要： A method and apparatus for calibrating failures in semiconductor memory devices due to contact mask misalignment includes: providing a plurality of semiconductor memory devices on a die; providing a contact mask with a plurality of known offsets; creating a plurality of contacts on the die using the contact mask; determining which devices on the die fail; and creating a pass/fail map for the devices. The pass/fail map can be used to determine the range of allowed misalignment and the amount of misalignment, providing a better understanding of how contact mask misalignment affects the yield and reliability of the memory devices. The pass/fail map may also be used for comparison with a pass/fail map created after the arrays have been subjected to a known stress.
摘要翻译：用于校准由于接触掩模未对准导致的半导体存储器件故障的方法和装置包括：在管芯上提供多个半导体存储器件; 提供具有多个已知偏移量的接触掩模; 使用所述接触掩模在所述管芯上产生多个接触; 确定模具上的哪些设备失效; 并为设备创建通过/失败映射。通过/失败映射可用于确定允许的未对准的范围和未对准的量，从而更好地了解接触掩模未对准如何影响存储器件的产量和可靠性。通过/失败映射也可用于与数组已经受到已知应力之后创建的通过/失败映射进行比较。

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