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1. 发明申请

US20150225737A1 Drought-Tolerance in Plants 审中-公开
标题翻译：植物耐旱性
公开(公告)号：US20150225737A1
公开(公告)日：2015-08-13
申请号：US14617061
申请日：2015-02-09
申请人： Kyung-Hwan Han , Won-Chan Kim , Joo-Yeol Kim , Jae-Heung Ko
发明人： Kyung-Hwan Han , Won-Chan Kim , Joo-Yeol Kim , Jae-Heung Ko
IPC分类号： C12N15/82
CPC分类号： C12N15/8273 , C12N15/113 , C12N15/8237
摘要： Drought-inducible plant promoters are described herein that are useful for expressing drought tolerance factors in plants.
摘要翻译：本文描述了可用于在植物中表达耐旱因子的干旱诱导型植物启动子。

2. 发明授权

US06556049B2 Output driver having output current compensation and method of compensating output current 有权
公开(公告)号：US06556049B2
公开(公告)日：2003-04-29
申请号：US09805210
申请日：2001-03-14
申请人： Yi-do Koo , Chang-sik Yoo , Kee-wook Jung , Won-chan Kim
发明人： Yi-do Koo , Chang-sik Yoo , Kee-wook Jung , Won-chan Kim
IPC分类号： H03K190175
CPC分类号： H03K19/00384 , H03K19/00361
摘要： An output driver supplying constant output current regardless of output voltage changes. The output driver includes a current source for regulating changes in a voltage of an output terminal responsive to a reference signal, and an output current compensator that responds to the current source to supply constant current to the terminal. The current source includes a first MOS transistor having a drain coupled to the terminal and a gate to which the reference signal is input, and a second MOS transistor having a drain coupled to a source of the first MOS transistor, a gate to which data is input, and a source coupled to ground. The current source may be an open drain current source. The output current compensator includes a current compensator coupled to the terminal, and a sensing driver for sensing voltage changes of the terminal and driving the current compensator.

3. 发明授权

US06535040B2 Duty cycle correction circuits that reduce distortion caused by mismatched transistor pairs 失效
标题翻译：减少由失配的晶体管对引起的失真的占空比校正电路
公开(公告)号：US06535040B2
公开(公告)日：2003-03-18
申请号：US09929522
申请日：2001-08-14
申请人： Yeon-jae Jung , Chang-sik Yoo , Kee-wook Jung , Won-chan Kim
发明人： Yeon-jae Jung , Chang-sik Yoo , Kee-wook Jung , Won-chan Kim
IPC分类号： H03K3017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.
摘要翻译：占空比校正电路包括占空比校正器和检测电路。占空比校正器响应于第一检测信号和具有第一占空比的第一控制信号产生具有比第一占空比更高的等效程度的第二占空比的第一输入信号。检测电路响应于第一输入信号产生第一检测信号。检测电路包括具有第一和第二电流源的电流源和电耦合到第一和第二电流源的偏置电路，并响应于第一输入信号控制第一和第二电流源的偏置。

4. 发明授权

US06483364B2 Ladder type clock network for reducing skew of clock signals 有权
标题翻译：梯形时钟网络，用于减少时钟信号的偏移
公开(公告)号：US06483364B2
公开(公告)日：2002-11-19
申请号：US09864190
申请日：2001-05-25
申请人： Young-don Choi , Chang-sik Yoo , Kee-wook Jung , Won-chan Kim
发明人： Young-don Choi , Chang-sik Yoo , Kee-wook Jung , Won-chan Kim
IPC分类号： G06F104
CPC分类号： H03K5/15013 , G06F1/10 , H03K5/135
摘要： A ladder type clock network for reducing the skew of clock signals is provided. The clock network includes a buffer for buffering a clock signal, first delay units for delaying the output of the first buffer by a set time, second buffers connected to respective outputs of the first delay units, and second delay units connected to respective outputs of the second buffers. The first delay units and the second delay units consist essentially of the resistance and capacitance of lines through which the clock signal propagates. Accordingly, the skew of the internal clock signals is reduced, and internal clock signals having a stable duty with respect to variations in a semiconductor device manufacturing process, temperature, and power supply voltage, are generated.
摘要翻译：提供了一种用于减少时钟信号偏斜的梯形时钟网络。时钟网络包括用于缓冲时钟信号的缓冲器，用于将第一缓冲器的输出延迟设定时间的第一延迟单元，连接到第一延迟单元的相应输出的第二缓冲器，以及连接到第一延迟单元的相应输出的第二延迟单元第二缓冲区。第一延迟单元和第二延迟单元基本上由时钟信号传播的线路的电阻和电容组成。因此，内部时钟信号的偏斜减小，并且产生相对于半导体器件制造工艺，温度和电源电压的变化具有稳定占空比的内部时钟信号。

5. 发明授权

US5656955A Low power output buffer circuit 失效
标题翻译：低功率输出缓冲电路
公开(公告)号：US5656955A
公开(公告)日：1997-08-12
申请号：US555854
申请日：1995-11-13
申请人： Sang-Hoon Chai , Won-Chul Song , Hoon-Bock Lee , Chang-Sik Yu , Won-Chan Kim
发明人： Sang-Hoon Chai , Won-Chul Song , Hoon-Bock Lee , Chang-Sik Yu , Won-Chan Kim
IPC分类号： H03K19/00 , H03K19/0185 , H03K19/0944
CPC分类号： H03K19/018528
摘要： A low power output buffer circuit for outputting an Emitter Coupled Logic(ECL) signal or Pseudo ECL(PECL) signal using a CMOS device is disclosed. The prior art differential output buffer circuit is comprised of two independent output buffer circuits and each output buffer circuit utilizes 50 ohms of the load resistors, having 20 mW of current to be applied to the circuit, which requires 100 mW of total consumptive power to operate the entire circuit. According to the present invention, a simplified output buffer circuit can be constructed by connecting 100 ohms of load resistors having a center tap to ground to two pads, which reduces half of the consumptive power as compared to that in the prior art circuit.
摘要翻译：公开了一种用于使用CMOS器件输出发射极耦合逻辑（ECL）信号或伪ECL（PECL）信号的低功率输出缓冲电路。现有技术的差分输出缓冲电路由两个独立的输出缓冲电路组成，每个输出缓冲电路利用50欧姆的负载电阻，其中20mW的电流被施加到电路上，这需要100mW的总消耗功率来操作整个电路。根据本发明，通过将具有中心抽头的100欧姆的负载电阻器连接到两个焊盘，可以构造简化的输出缓冲电路，与现有技术的电路相比，其减少了一半的消耗功率。

6. 发明授权

US06456122B1 Input buffer circuit for transforming pseudo differential signals into full differential signals 有权
标题翻译：输入缓冲电路，用于将伪差分信号变换为全差分信号
公开(公告)号：US06456122B1
公开(公告)日：2002-09-24
申请号：US09899223
申请日：2001-07-06
申请人： Joon-young Park , Chang-sik Yoo , Kee-wook Jung , Won-chan Kim
发明人： Joon-young Park , Chang-sik Yoo , Kee-wook Jung , Won-chan Kim
IPC分类号： G11C706
CPC分类号： H03K3/35613 , H03K5/2481 , H03K19/01721 , H03K19/018528
摘要： An input buffer circuit for transforming pseudo differential input signals into full differential output signals wherein, the input buffer circuit includes a pull-up current source, two pull-down current sources, a differential input portion, and a positive feedback portion. The pull-up current source is formed of two PMOS transistors which are always in an “on” state, and provides an electric current. The two pull-down current sources are each formed of an NMOS transistor, which are always in an on state, and sink a pull-up electric current. The differential input portion is formed of two NMOS transistors, and receives an input signal and a reference signal, respectively. The positive feedback portion is formed of two NMOS transistors, and enlarges a voltage difference between two output terminals of the input circuit using positive feedback.
摘要翻译：一种用于将伪差分输入信号变换为全差分输出信号的输入缓冲电路，其中，输入缓冲电路包括上拉电流源，两个下拉电流源，差分输入部分和正反馈部分。上拉电流源由总是处于“导通”状态的两个PMOS晶体管形成，并且提供电流。两个下拉电流源各自由NMOS晶体管形成，它们总是处于导通状态，并且吸收上拉电流。差分输入部分由两个NMOS晶体管构成，分别接收输入信号和参考信号。正反馈部分由两个NMOS晶体管形成，并且使用正反馈放大输入电路的两个输出端之间的电压差。

7. 发明申请

US20150133651A1 CslA9 Gluco-mannan Synthase Gene 有权
标题翻译： CslA9葡萄糖 - 甘露聚糖合酶基因
公开(公告)号：US20150133651A1
公开(公告)日：2015-05-14
申请号：US14540320
申请日：2014-11-13
申请人： KYUNG-HWAN HAN , WON-CHAN KIM , IDA-BARBARA RECA , KENNETH KEEGSTRA
发明人： KYUNG-HWAN HAN , WON-CHAN KIM , IDA-BARBARA RECA , KENNETH KEEGSTRA
IPC分类号： C12N15/82 , C07H1/08
CPC分类号： C12N15/8246 , C12N15/8217
摘要： The invention relates to plants that contain higher proportions of mannans. Such plants express transcription factors that increase the expression of CSLA9, a mannan synthase.
摘要翻译：本发明涉及含有较高比例甘露聚糖的植物。这种植物表达增加CSLA9（一种甘露聚糖合成酶）的表达的转录因子。

8. 发明申请

US20050163351A1 Semiconductor fingerprint sensing apparatus with shielding unit 审中-公开
标题翻译：具有屏蔽单元的半导体指纹感测装置
公开(公告)号：US20050163351A1
公开(公告)日：2005-07-28
申请号：US10506245
申请日：2002-06-12
申请人： Won-Chan Kim , Dong-Jin Min
发明人： Won-Chan Kim , Dong-Jin Min
IPC分类号： G06K9/00
CPC分类号： G06K9/0002
摘要： Disclosed is a semiconductor fingerprint sensing apparatus with a shielding unit for sensing an inherent pattern of a fingerprint by using minute difference of fingerprint impedance. This fingerprint sensing apparatus has the shielding unit between a charge supplying unit and a sensing electrode to prevent DC current from being directly applied to the human body through the sensing electrode. The fingerprint sensing apparatus also has a discharging unit for compulsorily discharging charges residual in the shielding unit and the sensing electrode, so the sensing electrode may be always charged at a regular level.
摘要翻译：公开了具有屏蔽单元的半导体指纹感测装置，用于通过使用指纹阻抗的微小差来感测指纹的固有模式。这种指纹感测装置具有在电荷供给单元和感测电极之间的屏蔽单元，以防止DC电流通过感测电极直接施加到人体。指纹检测装置还具有用于强制地对屏蔽单元和感测电极中的电荷残余放电的放电单元，因此感测电极可以总是以规律水平充电。

9. 发明申请

US20050163350A1 Fingerprint sensing apparatus and method using time-variable propertz of fingerpring signal 审中-公开
标题翻译：指纹感测装置和方法，使用指纹信号的时变特性
公开(公告)号：US20050163350A1
公开(公告)日：2005-07-28
申请号：US10506244
申请日：2002-06-12
申请人： Won-Chan Kim , Dong-Jin Min
发明人： Won-Chan Kim , Dong-Jin Min
IPC分类号： G06K9/00
CPC分类号： G06K9/0002
摘要： Disclosed are fingerprint sensing apparatus and method using a time-variable characteristic of a fingerprint signal which generates an analog fingerprint signal reflecting charging or discharging characteristic of fingerprint impedance by supplying or discharging electric charge to/from a sensing electrode and converts the analog signal into a digital value on the basis of time required for the analog fingerprint signal to reach a predetermined level. The fingerprint sensing apparatus may reproduce a specific fingerprint pattern at each sensing point by signaling the converted digital value.
摘要翻译：公开了使用指纹信号的时变特性的指纹感测装置和方法，其通过向/从感测电极提供或放电电荷来产生反映指纹阻抗的充电或放电特性的模拟指纹信号，并将模拟信号转换为基于模拟指纹信号达到预定水平所需的时间的数字值。指纹感测装置可以通过发信号转换的数字值来在每个感测点再现特定的指纹图案。

10. 发明授权

US06385126B2 Clock synchronization circuit and semiconductor device having the same 有权
标题翻译：时钟同步电路和具有该时钟同步电路的半导体器件
公开(公告)号：US06385126B2
公开(公告)日：2002-05-07
申请号：US09757792
申请日：2001-01-11
申请人： Yeon-jae Jung , Seung-wook Lee , Dae-yun Shim , Won-chan Kim
发明人： Yeon-jae Jung , Seung-wook Lee , Dae-yun Shim , Won-chan Kim
IPC分类号： G11C800
CPC分类号： G11C7/222 , G06F1/12 , G11C7/22 , G11C11/4076 , H03L7/07 , H03L7/0814 , H03L7/0893
摘要： A clock synchronization circuit is provided for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer adapted to output the internal clock signal. The circuit includes a first loop adapted to receive the external clock signal and output a plurality of reference clock signals having a predetermined phase difference therebetween. A second loop is adapted to delay the plurality of reference clock signals; select a signal from among the plurality of delayed reference clock signals; provide the selected signal to the clock buffer; detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal; generate a plurality of control voltages to reduce the detected phase difference, and control a delay amount of each of the plurality of reference clock signals in response to the plurality of control voltages; so as to synchronize the internal clock signal with the external clock signal.
摘要翻译：提供时钟同步电路，用于使外部时钟信号与内部时钟信号同步。该电路连接到适于输出内部时钟信号的时钟缓冲器。该电路包括适于接收外部时钟信号并输出其间具有预定相位差的多个参考时钟信号的第一回路。第二环路适于延迟多个参考时钟信号; 从所述多个延迟参考时钟信号中选择信号; 将选择的信号提供给时钟缓冲器; 检测从时钟缓冲器输出的内部时钟信号与外部时钟信号之间的相位差; 产生多个控制电压以减小检测到的相位差，并且响应于多个控制电压来控制多个参考时钟信号中的每一个的延迟量; 以使内部时钟信号与外部时钟信号同步。

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