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1. 发明授权

US4630096A High density IC module assembly 失效
标题翻译：高密度IC模块组装
公开(公告)号：US4630096A
公开(公告)日：1986-12-16
申请号：US615499
申请日：1984-05-30
申请人： James E. Drye , Jack A. Schroeder , Vern H. Winchell, II
发明人： James E. Drye , Jack A. Schroeder , Vern H. Winchell, II
IPC分类号： H05K3/30 , H01L23/053 , H01L23/14 , H01L23/538 , H01L25/04 , H01L25/18 , H01L29/06 , H01L23/12 , H01L23/18 , H01L23/40
CPC分类号： H01L23/053 , H01L23/147 , H01L23/538 , H01L24/24 , H01L2224/24137 , H01L2224/24227 , H01L2224/48091 , H01L2224/48472 , H01L2224/73265 , H01L24/48 , H01L29/0657 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01027 , H01L2924/01033 , H01L2924/01039 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10158 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15312 , H01L2924/18162 , H01L2924/19041 , H01L2924/3011 , H01L2924/351
摘要： An electronic module having a high density of silicon IC chips is provided by mounting the chips in tapered through-holes in a silicon substrate, filling the edge gaps between the chips and the substrate with a glass so that the chips, the filler glass, and the substrate have a smooth upper surface adapted to receive monolithic interconnections formed by planar metallization methods. The resulting assembly is enclosed in a housing also formed substantially from silicon, which contains electrically isolated pins for contacting the input-output electrodes of the assembly. Preferential etching is used to form the through-holes in the substrate as well as various alignment means on the substrate and other parts of the housing so that they are self-aligning during assembly. Improved performance, reliability, and low cost is obtained.
摘要翻译：通过将芯片安装在硅基板中的锥形通孔中来提供具有高密度硅IC芯片的电子模块，用玻璃填充芯片和基板之间的边缘间隙，使得芯片，填充玻璃和衬底具有适于接收由平面金属化方法形成的单片互连的平滑上表面。所得到的组件封装在基本上由硅形成的壳体中，该壳体包含用于接触组件的输入 - 输出电极的电隔离的销。使用优先蚀刻在基板中形成通孔以及在基板和壳体的其它部分上的各种对准装置，使得它们在组装期间自对准。获得了改进的性能，可靠性和低成本。

2. 发明授权

US4609936A Semiconductor chip with direct-bonded external leadframe 失效
标题翻译：半导体芯片采用直接外接引线框架
公开(公告)号：US4609936A
公开(公告)日：1986-09-02
申请号：US76878
申请日：1979-09-19
申请人： Thomas A. Scharr , Vern H. Winchell, II
发明人： Thomas A. Scharr , Vern H. Winchell, II
IPC分类号： H01L23/485 , H01L23/495 , H01L23/48 , H01L29/40 , H01L29/44
CPC分类号： H01L24/10 , H01L23/49548 , H01L24/13 , H01L2224/13 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/14
摘要： Structure and process for providing a hard metallic leadframe directly bonded to a semiconductor chip without the necessity for solder or soft intermediate leadframes. The structure provides a strong bond at the semiconductor chip with the possibility for multiple simultaneous lead attachment of a leadframe having sufficient strength to serve as the external leads. The bonded structure may be conventionally encapsulated in a plastic or ceramic package, or may be glassed to provide a minimum volume hermetic chip.
摘要翻译：用于提供直接接合到半导体芯片的硬金属引线框的结构和工艺，而不需要焊料或软的中间引线框架。该结构在半导体芯片处提供牢固的结合，具有用于多个同时引线连接引线框的可能性，其具有足够的强度以用作外部引线。粘合结构可以传统地封装在塑料或陶瓷封装中，或者可以被玻璃化以提供最小体积的密封芯片。

3. 发明授权

US4722914A Method of making a high density IC module assembly 失效
标题翻译：制造高密度IC模块组件的方法
公开(公告)号：US4722914A
公开(公告)日：1988-02-02
申请号：US896356
申请日：1986-08-13
申请人： James E. Drye , Jack A. Schroeder , Vern H. Winchell, II
发明人： James E. Drye , Jack A. Schroeder , Vern H. Winchell, II
IPC分类号： H01L23/053 , H01L23/14 , H01L23/538 , H01L29/06 , H01L21/56 , H01L23/30
CPC分类号： H01L23/147 , H01L23/053 , H01L23/538 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L29/0657 , H01L2924/01079 , H01L2924/10158 , H01L2924/10253 , H01L2924/14 , H01L2924/3011 , Y10T29/4913 , Y10T29/53178
摘要： An electronic module having a high density of silicon IC chips is provided by mounting the chips in tapered through-holes in a silicon substrate, filling the edge gaps between the chips and the substrate with a glass so that the chips, the filler glass, and the substrate have a smooth upper surface adapted to receive monolithic interconnections formed by planar metalization methods. The resulting assembly is enclosed in a housing also formed substantially from silicon, which contains electrically isolated pins for contacting the input-output electrodes of the assembly. Preferential etching is used to form the through-holes in the substrate as well as various alignment means on the substrate and other parts of the housing so that they are self-aligning during assembly. Improved performance, reliability, and low cost is obtained.
摘要翻译：通过将芯片安装在硅基板中的锥形通孔中来提供具有高密度硅IC芯片的电子模块，用玻璃填充芯片和基板之间的边缘间隙，使得芯片，填充玻璃和衬底具有适于接收由平面金属化方法形成的单片互连的平滑上表面。所得到的组件封装在基本上由硅形成的壳体中，该壳体包含用于接触组件的输入 - 输出电极的电隔离的销。使用优先蚀刻在基板中形成通孔以及在基板和壳体的其它部分上的各种对准装置，使得它们在组装期间自对准。获得了改进的性能，可靠性和低成本。

4. 发明授权

US5886362A Method of reflowing solder bumps after probe test 失效
标题翻译：探针测试后焊锡凸点的回流方法
公开(公告)号：US5886362A
公开(公告)日：1999-03-23
申请号：US161015
申请日：1993-12-03
申请人： Lavoie R. Millican , Vern H. Winchell, II
发明人： Lavoie R. Millican , Vern H. Winchell, II
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/014
摘要： An integrated circuit die is tested by inserting test probe needles into flat solder pads before reflow. The testing is performed at different temperatures to functionally test the integrated circuit die. The solder pads are flat during probe test to improve the uniform contact point and pressure for the test probes, and help avoid slippage or sliding. The probe needles may cause indentation in the solder pads. Following probe test, the solder pads are reflowed to transform the solder pads into solder bumps. Reflow after probe test removes any indentations from the solder pads created during the probe test and leaves only rounded solder bumps without probe damage. The solder bumps are used to flip-chip interconnect the IC into end user systems.
摘要翻译：通过在回流焊之前将测试针插入平坦焊盘来测试集成电路裸片。在不同的温度下进行测试以对集成电路管芯进行功能测试。在探针测试期间，焊盘是平坦的，以改善测试探针的均匀接触点和压力，并有助于避免滑动或滑动。探针可能会导致焊盘凹陷。在探针测试之后，焊盘被回流以将焊盘转换成焊料凸块。探针测试后的回流消除了在探针测试期间产生的焊盘的任何凹陷，并且仅留下没有探针损伤的圆形焊料凸块。焊锡凸块用于将IC倒装成最终用户系统。

5. 发明授权

US5164885A Electronic package having a non-oxide ceramic bonded to metal and method for making 失效
标题翻译：具有与金属结合的非氧化物陶瓷的电子封装及其制造方法
公开(公告)号：US5164885A
公开(公告)日：1992-11-17
申请号：US795441
申请日：1991-11-21
申请人： James E. Drye , David J. Reed , Vern H. Winchell, II
发明人： James E. Drye , David J. Reed , Vern H. Winchell, II
IPC分类号： H01L23/15 , H01L23/367 , H01L23/495
CPC分类号： H01L23/15 , H01L23/367 , H01L23/49541 , H01L24/49 , H01L2224/48091 , H01L2224/49 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/30105 , Y10T29/49002 , Y10T29/49144
摘要： A non-oxide ceramic (16) for electronic packages and a method of producing electronic packages using a non-oxide ceramic is provided. In accordance with the present invention, the non-oxide ceramic (16) is coated with silicon dioxide (15) and a bonding glass (14) having diboron trioxide is used to attach other package components such as semiconductor chips (18), leadframes (13), and heatsinks (11) to the non-oxide ceramic (16).
摘要翻译：提供一种用于电子封装的非氧化物陶瓷（16）和使用非氧化物陶瓷生产电子封装的方法。根据本发明，非氧化物陶瓷（16）涂覆有二氧化硅（15），并且使用具有三氧化二硼的粘合玻璃（14）来附接其它封装部件，例如半导体芯片（18），引线框架 13）和散热器（11）到非氧化物陶瓷（16）。

6. 发明授权

US4394678A Elevated edge-protected bonding pedestals for semiconductor devices 失效
标题翻译：用于半导体器件的高边缘保护接合基座
公开(公告)号：US4394678A
公开(公告)日：1983-07-19
申请号：US76879
申请日：1979-09-19
申请人： Vern H. Winchell, II , Thomas A. Scharr , Lowell E. Clark
发明人： Vern H. Winchell, II , Thomas A. Scharr , Lowell E. Clark
IPC分类号： H01L23/485 , H01L23/48 , H01L29/44 , H01L29/52
CPC分类号： H01L24/05 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/12036 , H01L2924/14 , H01L2924/30105
摘要： An elevated bonding pad suitable for wire or lead frame attachment and having an insulating layer completely over its outer periphery. The structure simplifies the processing required to form an elevated bonding pad, and serves to protect the periphery against bonding damage, and provides protection against corrosion of the bonded encapsulated semiconductor unit.
摘要翻译：一种适用于电线或引线框架连接的升高的焊盘，其绝缘层完全在其外周上。该结构简化了形成升高的焊盘所需的处理，并且用于保护周边免受接合损坏，并提供防止粘合的封装的半导体单元的腐蚀的保护。

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