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    • 1. 发明授权
    • Method and apparatus for providing switch-based features
    • 用于提供基于开关的特征的方法和装置
    • US5521919A
    • 1996-05-28
    • US334308
    • 1994-11-04
    • Thomas W. AndersonThomas E. BowersCharles C. Byers
    • Thomas W. AndersonThomas E. BowersCharles C. Byers
    • H04M3/00H04M3/40H04Q11/04H04Q11/08
    • H04M3/002H04M3/40H04Q11/04
    • A system and method to provide voice enhancement circuits on a voice path on an individual basis, without having in-line circuits inserted into the lines or trunks. The enhancement circuit is inserted within one or more of the switches. This system comprises a switching system having a switching fabric and a central control, wherein the switching fabric includes several extended time slot interchange (XTSI) units connected to a time multiplex switch. The extended time slot interchange unit has approximately twice the capacity of a standard time slot interchange unit. Such XTSI is connected to voice enhancing circuits, which the TSI may then switch enhancement circuits into a call path. A method of setting up a call according to this invention includes routing the call to a switch, routing the call in the switch into an XTSI, which routes a call through the enhancement circuit, and then back through the XTSI.
    • 在单独的语音路径上提供语音增强电路的系统和方法,而不会将线内电路插入到线路或中继线中。 增强电路插入在一个或多个开关内。 该系统包括具有交换结构和中央控制的交换系统,其中交换结构包括连接到时间复用交换机的几个扩展时隙交换(XTSI)单元。 扩展时隙交换单元具有标准时隙交换单元容量的大约两倍。 这样的XTSI连接到语音增强电路,TSI然后可以将增强电路切换成呼叫路径。 根据本发明的建立呼叫的方法包括将呼叫路由到交换机,将交换机中的呼叫路由到XTSI,其通过增强电路路由呼叫,然后通过XTSI返回。
    • 4. 发明授权
    • Phase locked loop for deriving clock signal from aperiodic data signal
    • 用于从非周期性数据信号中导出时钟信号的锁相环
    • US4222013A
    • 1980-09-09
    • US963270
    • 1978-11-24
    • Thomas E. BowersDennis E. Tomlinson
    • Thomas E. BowersDennis E. Tomlinson
    • H03L7/089H04L7/033H03B3/04
    • H04L7/033H03L7/089
    • A phase locked loop circuit (100) for generating a periodic clock signal from a controlled oscillator circuit (130) in phase coincidence with a synchronous aperiodic data input signal is disclosed. A pulse of the data signal and a corresponding pulse of the clock signal are applied to a bistable circuit (FF1) having an output signal indicating which of the pulses occurs first in time. The pulses are further applied through delay circuitry (DLY1, DLY2) to another bistable circuit (FF2) having an output signal indicative of the magnitude of phase difference between the pulses. The output signals of the bistable circuits (FF1, FF2) are applied to a multilevel driver circuit (140) which generates an error correction signal pulse defining magnitude and direction of a correction signal to be applied to the oscillator circuit (130).
    • 公开了一种用于从受控振荡器电路(130)产生与同步非周期数据输入信号相位一致的周期性时钟信号的锁相环电路(100)。 数据信号的脉冲和时钟信号的对应脉冲被施加到具有指示在时间上首先发生哪些脉冲的输出信号的双稳态电路(FF1)。 脉冲进一步通过延迟电路(DLY1,DLY2)施加到具有指示脉冲之间的相位差大小的输出信号的另一双稳态电路(FF2)。 双稳态电路(FF1,FF2)的输出信号被施加到多电平驱动电路(140),该电平产生纠正信号脉冲,该纠错信号脉冲定义要施加到振荡电路(130)的校正信号的幅度和方向。