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1. 发明授权

US09112067B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09112067B2
公开(公告)日：2015-08-18
申请号：US12766389
申请日：2010-04-23
申请人： Teruyuki Fujii , Kohei Ohshima , Junya Maruyama , Akihisa Shimomura
发明人： Teruyuki Fujii , Kohei Ohshima , Junya Maruyama , Akihisa Shimomura
IPC分类号： H01L31/0224 , H01L31/0296 , H01L31/02 , H01L31/028 , H01L31/068 , H01L31/075
CPC分类号： H01L31/022425 , H01L31/02008 , H01L31/028 , H01L31/0296 , H01L31/068 , H01L31/075 , Y02E10/50
摘要： An object relates to an electrode of a semiconductor device or a method for manufacturing a semiconductor device, which includes a bonding step, and problems are: (1) high resistance of a semiconductor device due to the use of an Al electrode, (2) formation of an alloy by Al and Si, (3) high resistance of a film formed by a sputtering method, and (4) defective bonding in a bonding step which is caused if a bonding surface has a large unevenness. A semiconductor device includes a metal substrate or a substrate provided with a metal film, a copper (Cu) plating film over and bonded to the metal substrate or the metal film by employing a thermocompression bonding method, a barrier film over the Cu plating film, a single crystal silicon film over the barrier film, and an electrode layer over the single crystal silicon film.
摘要翻译：本发明涉及一种半导体器件的电极或半导体器件的制造方法，其包括接合工序，其问题是：（1）由于使用Al电极而导致的半导体器件的高电阻，（2）通过Al和Si形成合金，（3）通过溅射法形成的膜的高电阻，以及（4）如果接合表面具有大的不平坦度时引起的接合步骤中的不良接合。半导体装置包括金属基板或具有金属膜的金属基板，通过使用热压接法在金属基板或金属膜上结合的铜（Cu）电镀膜，在Cu镀膜上的阻挡膜，阻挡膜上的单晶硅膜，以及单晶硅膜上的电极层。

2. 发明授权

US09917109B2 Semiconductor device 有权
公开(公告)号：US09917109B2
公开(公告)日：2018-03-13
申请号：US13039450
申请日：2011-03-03
申请人： Teruyuki Fujii , Ryota Imahayashi
发明人： Teruyuki Fujii , Ryota Imahayashi
IPC分类号： H01L29/10 , H01L27/12
CPC分类号： H01L27/1225 , H01L27/124
摘要： A semiconductor device includes a wiring embedded in an insulating layer, an oxide semiconductor layer over the insulating layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate electrode provided to overlap with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode. The insulating layer is formed so that part of a top surface of the wiring is exposed. The part of the top surface of the wiring is positioned higher than part of a surface of the insulating layer. The wiring in a region exposed from the insulating layer is electrically connected to the source electrode or the drain electrode. The root-mean-square roughness of a region which is part of the surface of the insulating layer and in contact with the oxide semiconductor layer is 1 nm or less.

3. 发明申请

US20120193435A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120193435A1
公开(公告)日：2012-08-02
申请号：US13361988
申请日：2012-01-31
申请人： Kazuya HANAOKA , Hideto Ohnuma , Teruyuki Fujii
发明人： Kazuya HANAOKA , Hideto Ohnuma , Teruyuki Fujii
IPC分类号： G06K19/077
CPC分类号： H01Q1/2208 , H01Q9/0407 , H01Q23/00
摘要： An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over one substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over one substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to decrease an adverse effect on electrical characteristics of circuit elements due to copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal.
摘要翻译：本发明的目的是为了防止在具有集成电路的半导体器件中的电路元件的电气特性受到不利影响，并且在一个衬底上形成天线，该衬底使用用于天线的铜电镀。另一个目的是防止在具有集成电路的半导体器件中的天线与集成电路之间的不良连接导致半导体器件的缺陷，并且形成在一个衬底上的天线。在具有集成电路100和在一个基板102上形成的天线101的半导体器件中，当将铜镀层108用于天线101的导体时，可以减少对电路元件的电特性的不利影响，由于天线101的基极层107使用预定金属的氮化物膜而导致铜扩散。

4. 发明授权

US08084081B2 Lighting emitting device, manufacturing method of the same, electronic apparatus having the same 有权
标题翻译：照明发光装置及其制造方法，具有该照明装置的电子设备
公开(公告)号：US08084081B2
公开(公告)日：2011-12-27
申请号：US11695110
申请日：2007-04-02
申请人： Teruyuki Fujii , Shunpei Yamazaki
发明人： Teruyuki Fujii , Shunpei Yamazaki
IPC分类号： B05D5/06
CPC分类号： H01L27/3251 , G06F1/1637 , G09G3/3225 , G09G2300/08 , G09G2320/0626 , G09G2380/14 , H01L25/0753 , H01L27/156 , H01L27/3246 , H01L27/3267 , H01L31/0232 , H01L33/08 , H01L33/44 , H01L33/502 , H01L33/60 , H01L51/0011 , H01L51/5012 , H01L51/5237 , H01L51/5246 , H01L51/5253 , H01L51/5262 , H01L2251/558 , H01L2924/0002 , Y10T428/24942 , H01L2924/00
摘要： One pixel is divided into a first region including a first light emitting element and a second region including a second light emitting element, wherein the first region emits light in one direction and the second region emits light in the direction opposite to that of the first region. Independently driving the first light emitting element and the second light emitting element allows images to be displayed independently on the surface.
摘要翻译：一个像素被分成包括第一发光元件的第一区域和包括第二发光元件的第二区域，其中第一区域在一个方向上发光，而第二区域沿与第一区域相反的方向发光。独立地驱动第一发光元件和第二发光元件允许在表面上独立地显示图像。

5. 发明授权

US07220603B2 Method for manufacturing display device and manufacturing apparatus 有权
标题翻译：显示装置及制造装置的制造方法
公开(公告)号：US07220603B2
公开(公告)日：2007-05-22
申请号：US10941687
申请日：2004-09-15
申请人： Yoshiharu Hirakata , Kaoru Tsuchiya , Tomoyuki Iwabuchi , Teruyuki Fujii , Shunpei Yamazaki
发明人： Yoshiharu Hirakata , Kaoru Tsuchiya , Tomoyuki Iwabuchi , Teruyuki Fujii , Shunpei Yamazaki
IPC分类号： H01L21/00
CPC分类号： H01L51/56 , G09G3/3208 , G09G2310/0256 , G09G2320/043 , H01L27/1214 , H01L51/524 , H01L2251/568
摘要： It is an object of the present invention to provide a method of manufacturing a display device, which can display images favorably by insulating a short-circuit portion between an anode and a cathode. Further, it is another object of the invention to provide a method of manufacturing a display device, which can prevent intrusion of moisture so as to inhibit deterioration of a light emitting element when the short-circuit portion between the anode and the cathode is insulated. Specifically, the invention provide a method of manufacturing a display device, wherein a reverse bias voltage is applied to the light emitting element including an electro-luminescent material between the anode and the cathode so as to insulate the short-circuit portion between the anode and the cathode at a temperature of from −40° C. to 8° C., more preferably, from −25° C. to 8° C.
摘要翻译：本发明的目的是提供一种制造显示装置的方法，其可以通过绝缘阳极和阴极之间的短路部分来显示图像。此外，本发明的另一个目的是提供一种制造显示装置的方法，其可以防止水分的侵入，从而当阳极和阴极之间的短路部分被绝缘时，抑制发光元件的劣化。具体地说，本发明提供一种制造显示装置的方法，其中在阳极和阴极之间向发光元件施加包括电致发光材料的反向偏置电压，以使阳极与阴极之间的短路部分绝缘，阴极在-40℃至8℃的温度下，更优选在-25℃至8℃。

6. 发明授权

US07750852B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07750852B2
公开(公告)日：2010-07-06
申请号：US12055918
申请日：2008-03-26
申请人： Kazuya Hanaoka , Hideto Ohnuma , Teruyuki Fujii
发明人： Kazuya Hanaoka , Hideto Ohnuma , Teruyuki Fujii
IPC分类号： H01Q1/38
CPC分类号： H01Q1/2208 , H01Q9/0407 , H01Q23/00
摘要： An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over the same substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over the same substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to prevent copper diffusion to circuit elements and decrease an adverse effect on electrical characteristics of circuit elements due to the copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal. Moreover, by the use of nickel nitride as a metal nitride for the base layer of the antenna, poor connection between the antenna and the integrated circuit can be decreased.
摘要翻译：本发明的目的是为了防止电路元件的电特性在具有集成电路的半导体器件和形成在同一衬底上的天线的铜扩散的不利影响，该天线使用用于天线的铜电镀。另一个目的是防止由于在具有集成电路的半导体器件中的天线和集成电路之间的连接不良而导致半导体器件的缺陷，并且天线形成在同一衬底上。在具有形成在一个基板102上的集成电路100和天线101的半导体器件中，当将铜镀层108用于天线101的导体时，可以防止铜扩散到电路元件并降低不利影响由于铜扩散而导致的电路元件的电特性，因为天线101的基极层107使用预定金属的氮化物膜。此外，通过使用氮化镍作为天线的基底层的金属氮化物，可以降低天线与集成电路之间的不良连接。

7. 发明申请

US20090246953A1 Method for Manufacturing Semiconductor Device 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20090246953A1
公开(公告)日：2009-10-01
申请号：US12477303
申请日：2009-06-03
申请人： Satoru Okamoto , Teruyuki Fujii , Hideto Ohnuma , Akihiro Ishizuka
发明人： Satoru Okamoto , Teruyuki Fujii , Hideto Ohnuma , Akihiro Ishizuka
IPC分类号： H01L21/3205 , H01L21/3065 , H01L21/306 , H01L21/308
CPC分类号： H01L27/124 , C23F1/20 , C23F1/26 , G02F1/136227 , G02F2001/13629 , H01L21/32134 , H01L21/32136 , H01L21/76838 , H01L21/76885
摘要： It is an object of the present invention to provide a semiconductor device including a wiring having a preferable shape. A manufacturing method includes the steps of forming a first conductive layer connected to an element and a second conductive layer thereover; forming a resist mask over the second conductive layer; processing the second conductive layer by dry etching with the use of the mask; and processing the first conductive layer by wet etching with the mask left, wherein the etching rate of the second conductive layer is higher than that of the first conductive layer in the dry etching, and wherein the etching rate of the second conductive layer is the same as or more than that of the first conductive layer in the wet etching.
摘要翻译：本发明的目的是提供一种包括具有优选形状的布线的半导体器件。一种制造方法包括以下步骤：形成连接到元件的第一导电层和其上的第二导电层; 在所述第二导电层上形成抗蚀剂掩模; 通过使用掩模的干法蚀刻处理第二导电层; 以及通过左蚀刻法进行湿式蚀刻来处理第一导电层，其中在干蚀刻中第二导电层的蚀刻速率高于第一导电层的蚀刻速率，并且其中第二导电层的蚀刻速率相同等于或大于湿蚀刻中第一导电层的厚度。

8. 发明申请

US20070287207A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070287207A1
公开(公告)日：2007-12-13
申请号：US11806870
申请日：2007-06-05
申请人： Teruyuki Fujii
发明人： Teruyuki Fujii
IPC分类号： H01L21/00
CPC分类号： H01L27/3246 , H01L27/3283 , H01L51/56
摘要： An object is to provide a semiconductor device with excellent reproducibility which is manufactured at low cost. A manufacturing method of a semiconductor device includes steps of forming a first electrode over a substrate; forming an insulating layer over the substrate and the first electrode; pressing a mold against the insulating layer to form an opening in the insulating layer; separating the mold from the insulating layer in which the opening is formed; hardening the insulating layer in which the opening is formed to form a partition wall; forming a light-emitting layer over the first electrode and the partition wall; and forming a second electrode over the light-emitting layer. The insulating layer contains a thermosetting resin material or a light curable resin material. The partition wall has a cross-sectional taper angle of 20 to 50°, and edges of a top and bottom thereof are rounded.
摘要翻译：目的在于提供以低成本制造的具有优异再现性的半导体器件。半导体器件的制造方法包括以下步骤：在衬底上形成第一电极; 在所述基板和所述第一电极上形成绝缘层; 将模具压在绝缘层上以在绝缘层中形成开口; 将模具与形成开口的绝缘层分离; 硬化其中形成开口的绝缘层以形成分隔壁; 在所述第一电极和所述分隔壁上形成发光层; 以及在所述发光层上形成第二电极。绝缘层包含热固性树脂材料或光固化树脂材料。分隔壁的截面锥角为20〜50°，其顶部和底部的边缘为圆形。

9. 发明申请

US20050245078A1 Manufacturing method of display device and semiconductor device 有权
标题翻译：显示器件和半导体器件的制造方法
公开(公告)号：US20050245078A1
公开(公告)日：2005-11-03
申请号：US11114870
申请日：2005-04-26
申请人： Hideto Ohnuma , Kiyofumi Ogino , Teruyuki Fujii
发明人： Hideto Ohnuma , Kiyofumi Ogino , Teruyuki Fujii
IPC分类号： H01L21/44 , H01L21/77
CPC分类号： H01L27/1292
摘要： It is an object of the present invention to improve the surface planarity of a film by uniforming the thickness of an insulating layer. Further, it is another object of the invention to provide a technology for manufacturing an electronic device typified by a high-definition and high-quality display device with high yield at low cost with the use of the insulating layer. In a method for manufacturing a semiconductor device according to the invention, a semiconductor layer is formed; an insulating layer is formed over the semiconductor layer; a wiring layer connected to the semiconductor layer is formed in an opening provided in the insulating layer; and an electrode layer connected to the wiring layer is formed. The insulating layer is formed by spin coating with a composition containing an insulating material, which has a viscosity of from 10 mP·s to 50 mP·s.
摘要翻译：本发明的目的是通过使绝缘层的厚度均匀化来改善膜的表面平坦度。此外，本发明的另一个目的是提供一种使用绝缘层以低成本制造高清晰度和高质量显示装置的电子装置的制造技术。在根据本发明的半导体器件的制造方法中，形成半导体层; 在半导体层上形成绝缘层; 连接到半导体层的布线层形成在设置在绝缘层中的开口中; 形成与布线层连接的电极层。绝缘层通过使用粘合剂为10mP.s至50mP.s.的包含绝缘材料的组合物进行旋涂而形成。

10. 发明授权

US6075390A Key interface circuit with reduced number of input terminals 失效
标题翻译：键接口电路，输入端数量少
公开(公告)号：US6075390A
公开(公告)日：2000-06-13
申请号：US69941
申请日：1998-04-30
申请人： Yasuhiro Shin , Teruyuki Fujii
发明人： Yasuhiro Shin , Teruyuki Fujii
IPC分类号： G06F3/023 , H03M11/20 , H03M11/24 , H03K5/22
CPC分类号： H03M11/24
摘要： A static key interface circuit has an input terminal coupled to N key switches, where N is an integer greater than one. The N key switches are biased at different potentials, which are supplied to the input terminal when the key switches are closed. A multilevel detector in the key interface circuit detects the potential of the input terminal and generates corresponding result data. A dynamic key interface circuit has an input terminal coupled to P rows of N key switches each and scans the P rows in turn, using a similar multilevel detector. The multilevel detector increases the number of key switches connectable to a single input terminal by a factor of N.
摘要翻译：静态键接口电路具有耦合到N个键开关的输入端，其中N是大于1的整数。 N键开关偏置在不同的电位，当钥匙开关闭合时，它们被提供给输入端。键接口电路中的多电平检测器检测输入端子的电位，并产生相应的结果数据。动态键接口电路具有一个输入端，其耦合到P行的N个键开关，并且使用类似的多电平检测器依次扫描P行。多级检测器将可连接到单个输入端子的键开关的数量增加N倍。

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