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1. 发明授权

US5276340A Semiconductor integrated circuit having a reduced side gate effect 失效
标题翻译：具有减小的侧栅效应的半导体集成电路
公开(公告)号：US5276340A
公开(公告)日：1994-01-04
申请号：US976000
申请日：1992-11-13
申请人： Teruo Yokoyama , Masahisa Suzuki , Tomonori Ishikawa , Takeshi Igarashi
发明人： Teruo Yokoyama , Masahisa Suzuki , Tomonori Ishikawa , Takeshi Igarashi
IPC分类号： H01L21/20 , H01L21/76 , H01L27/095 , H01L29/10 , H01L29/20 , H01L29/32 , H01L29/161 , H01L29/205 , H01L29/225
CPC分类号： H01L29/32 , H01L21/7605 , H01L27/095 , H01L29/1075 , H01L29/20 , H01L21/02395 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/02631
摘要： A semiconductor integrated circuit including therein a plurality of active devices comprises a semiconductor substrate, a first buffer layer on the substrate, a second buffer layer provided on the substrate and incorporating therein defects with a concentration level substantially larger than the concentration level of the defects in the first buffer layer; a device layer provided on the second buffer layer and being provided with the active devices, and a plurality of unconductive, device isolation regions formed between the active devices such that the device isolation region extends from an upper surface of the device layer toward the substrate at least beyond a lower surface of the device layer.
摘要翻译：其中包括多个有源器件的半导体集成电路包括半导体衬底，衬底上的第一缓冲层，设置在衬底上的第二缓冲层，并且其中包含浓度级明显大于缺陷浓度水平的缺陷第一缓冲层; 设置在第二缓冲层上并且设置有有源器件的器件层，以及形成在有源器件之间的多个不导电的器件隔离区域，使得器件隔离区域从器件层的上表面朝向衬底延伸最少超过器件层的下表面。

2. 发明授权

US5686325A Method for forming MESFET having T-shaped gate electrode 失效
标题翻译：用于形成具有T形栅电极的MESFET的方法
公开(公告)号：US5686325A
公开(公告)日：1997-11-11
申请号：US531981
申请日：1995-09-21
申请人： Toshiaki Moriuchi , Teruo Yokoyama
发明人： Toshiaki Moriuchi , Teruo Yokoyama
IPC分类号： H01L21/28 , H01L21/285 , H01L21/316 , H01L21/338 , H01L29/423 , H01L29/47 , H01L29/778 , H01L29/812 , H01L21/265
CPC分类号： H01L29/66871 , H01L21/28587 , H01L29/42316 , H01L29/475 , H01L29/7787 , H01L29/812 , Y10S148/10 , Y10S438/951
摘要： A compound semiconductor transistor has a structure in which a first insulating film is formed only under a overhang of a gate electrode an upper part of which is formed widely, and a second insulating film for threshold voltage adjustment is formed on the side of a gate electrode and the first insulating film.
摘要翻译：化合物半导体晶体管具有这样的结构，其中第一绝缘膜仅形成在其上部被广泛形成的栅电极的突出部下方，并且用于阈值电压调节的第二绝缘膜形成在栅电极侧和第一绝缘膜。

3. 发明授权

US6153897A Heterojunction compound semiconductor device and method of manufacturing the same 失效
标题翻译：异质结复合半导体器件及其制造方法
公开(公告)号：US6153897A
公开(公告)日：2000-11-28
申请号：US145287
申请日：1998-09-02
申请人： Hiroyuki Oguri , Teruo Yokoyama
发明人： Hiroyuki Oguri , Teruo Yokoyama
IPC分类号： C23F4/00 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/335 , H01L21/8252 , H01L27/06 , H05H1/46 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01J37/32972 , C23F4/00 , H01L21/30621 , H01L21/8252 , H01L27/0605 , H01L29/66462
摘要： A laminated layer having a layer containing Al (In) and a layer not containing Al (In) alternately laminated one upon another is plasma etched by an etchant gas which can etch both the layers containing and not containing Al (In). An additive gas containing F is added to the etchant gas while a layer not containing Al (In) is etched. When the surface of the layer containing Al (In) is exposed, fluorides are formed on the surface of the layer containing Al (In) and the etching is automatically stopped. An emission peak specific to Al (In) is monitored to detect which layer is presently etched.
摘要翻译：具有交替层叠的包含Al（In）的层和不含Al（In）的层的层叠层通过蚀刻剂气体进行等离子体蚀刻，蚀刻剂气体可以蚀刻含有并且不含Al（In）的两层。将含有F的添加气体添加到蚀刻剂气体中，同时不含Al（In）的层被蚀刻。当含有Al（In）的层的表面暴露时，在包含Al（In）的层的表面上形成氟化物，并且蚀刻自动停止。监测特定于Al（In）的发射峰，以检测目前蚀刻的层。

4. 发明授权

US6075262A Semiconductor device having T-shaped gate electrode 失效
标题翻译：具有T形栅电极的半导体器件
公开(公告)号：US6075262A
公开(公告)日：2000-06-13
申请号：US900874
申请日：1997-07-25
申请人： Toshiaki Moriuchi , Teruo Yokoyama
发明人： Toshiaki Moriuchi , Teruo Yokoyama
IPC分类号： H01L21/285 , H01L21/338 , H01L29/423 , H01L29/778 , H01L29/812 , H01L21/203
CPC分类号： H01L29/66878 , H01L21/28587 , H01L29/42316 , H01L29/7787 , H01L29/812
摘要： A compound semiconductor transistor has a structure in which a first insulating film is formed only under a overhang of a gate electrode an upper part of which is formed widely, and a second insulating film for threshold voltage adjustment is formed on the side of a gate electrode and the first insulating film.
摘要翻译：化合物半导体晶体管具有这样的结构，其中第一绝缘膜仅形成在其上部被广泛形成的栅电极的突出部下方，并且用于阈值电压调节的第二绝缘膜形成在栅电极侧和第一绝缘膜。

5. 发明授权

US06329677B1 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US06329677B1
公开(公告)日：2001-12-11
申请号：US09330087
申请日：1999-06-11
申请人： Hiroyuki Oguri , Teruo Yokoyama
发明人： Hiroyuki Oguri , Teruo Yokoyama
IPC分类号： H01L310328
CPC分类号： H01L29/7783 , H01L21/2636 , H01L21/268 , H01L29/0843 , H01L29/812
摘要： A field effect transistor has a semiconductor lamination structure, a Schottky contact gate electrode and source/drain ohmic electrodes disposed on both sides of the gate electrode on the lamination structure, source/drain regions disposed under the source/drain electrodes, a channel layer disposed in the lamination structure spaced apart from the principal surface and connecting the source/drain regions, a barrier layer disposed in the lamination structure between the channel layer and the principal surface and having a conduction band edge energy higher than the channel layer, and a pair of impurity doped regions formed in the barrier layer and channel layer continuously with the source/drain regions on both sides of the gate electrode, wherein a carrier density in the barrier layer is lower than a carrier density in the channel layer in the impurity doped region. A filed effect transistor and its manufacture method are provided which can lower the source resistance of the field effect transistor while the gate breakdown voltage is maintained high.
摘要翻译：场效应晶体管具有半导体层叠结构，肖特基接触栅电极和设置在层叠结构上的栅电极两侧的源极/漏极欧姆电极，设置在源极/漏极下方的源极/漏极区，设置在沟道层在与主表面间隔开并连接源极/漏极区域的层叠结构中，设置在层叠结构中的沟道层和主表面之间并且具有比沟道层高的导带边缘能量的势垒层，以及一对形成在阻挡层和沟道层中的杂质掺杂区域与栅极两侧的源极/漏极区域连续，其中阻挡层中的载流子密度低于杂质掺杂区域中的沟道层中的载流子密度。提供了一种场效应晶体管及其制造方法，其可以在栅极击穿电压保持为高的同时降低场效应晶体管的源极电阻。

6. 发明授权

US06395588B2 Compound semiconductor device and method of manufacturing the same 有权
标题翻译：化合物半导体器件及其制造方法
公开(公告)号：US06395588B2
公开(公告)日：2002-05-28
申请号：US09880867
申请日：2001-06-15
申请人： Tsutomu Igarashi , Kenji Arimochi , Teruo Yokoyama , Eizo Mitani , Shigeru Kuroda , Junichiro Nikaido , Yasunori Tateno
发明人： Tsutomu Igarashi , Kenji Arimochi , Teruo Yokoyama , Eizo Mitani , Shigeru Kuroda , Junichiro Nikaido , Yasunori Tateno
IPC分类号： H01L21338
CPC分类号： H01L29/7783 , H01L29/1029
摘要： The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1˜1016 to 1˜1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer. Otherwise, in the steps of manufacturing the high electron mobility field effect transistor, after a silicon nitride film has been formed on a GaAs buried layer in which a second recess is formed and in a region on the inside of a first recess formed in a GaAs contact layer, the GaAs buried layer is still heated.
摘要翻译：包含在高电子迁移率场效应晶体管的电子供给层上的层中的杂质浓度设定在1〜1016〜1〜1017原子/ cm3的范围内，或者将肖特基层的带隙设定为宽于电子供应层。否则，在制造高电子迁移率场效应晶体管的步骤中，在形成有第二凹部的GaAs掩埋层上形成氮化硅膜之后，在形成于GaAs的第一凹部的内部的区域接触层，GaAs掩埋层仍然加热。

7. 发明授权

US06274893B1 Compound semiconductor device and method of manufacturing the same 有权
标题翻译：化合物半导体器件及其制造方法
公开(公告)号：US06274893B1
公开(公告)日：2001-08-14
申请号：US09330085
申请日：1999-06-11
申请人： Tsutomu Igarashi , Kenji Arimochi , Teruo Yokoyama , Eizo Mitani , Shigeru Kuroda , Junichiro Nikaido , Yasunori Tateno
发明人： Tsutomu Igarashi , Kenji Arimochi , Teruo Yokoyama , Eizo Mitani , Shigeru Kuroda , Junichiro Nikaido , Yasunori Tateno
IPC分类号： H01L31072
CPC分类号： H01L29/7783 , H01L29/1029
摘要： The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1×1016 to 1×1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer.
摘要翻译：包含在高电子迁移率场效应晶体管的电子供给层上的层中的杂质浓度设定在1×1016至1×1017原子/ cm3的范围内，或者将肖特基层的带隙设置为比电子供给层的带隙宽。

8. 发明授权

US5837617A Heterojunction compound semiconductor device and method of manufacturing the same 失效
公开(公告)号：US5837617A
公开(公告)日：1998-11-17
申请号：US221900
申请日：1994-04-01
申请人： Hiroyuki Oguri , Teruo Yokoyama
发明人： Hiroyuki Oguri , Teruo Yokoyama
IPC分类号： C23F4/00 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/335 , H01L21/8252 , H01L27/06 , H05H1/46
CPC分类号： H01J37/32972 , C23F4/00 , H01L21/30621 , H01L21/8252 , H01L27/0605 , H01L29/66462
摘要： A laminated layer having a layer containing Al (In) and a layer not containing Al (In) alternately laminated one upon another is plasma etched by an etchant gas which can etch both the layers containing and not containing Al (In). An additive gas containing F is added to the etchant gas while a layer not containing Al (In) is etched. When the surface of the layer containing Al (In) is exposed, fluorides are formed on the surface of the layer containing Al (In) and the etching is automatically stopped. An emission peak specific to Al (In) is monitored to detect which layer is presently etched.

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