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1. 发明授权

US5657469A Selective access to divided word line segments in cache memory 失效
标题翻译：选择性地访问缓存中的分割字段
公开(公告)号：US5657469A
公开(公告)日：1997-08-12
申请号：US549073
申请日：1995-10-27
申请人： Tamio Shimizu
发明人： Tamio Shimizu
IPC分类号： G11C11/401 , G06F12/08 , G11C8/14 , G11C11/406 , G11C11/407 , G11C11/409 , G11C15/00 , G06F12/04
CPC分类号： G11C8/14 , G06F12/0893 , G11C15/00
摘要： A DRAM using a divided word line scheme has a cache operation capability. A cache line has a data corresponding to sub-block data. Each data set of sub-block is related to the individual main word address. The DRAM has an extra data storage for selecting a data transfer mode between a sense latch and the storage. With the storage, the DRAM is capable of transferring a plurality of data sets having different row addresses to the sense latch at the same time.
摘要翻译：使用分割字线方案的DRAM具有高速缓存操作能力。高速缓存行具有对应于子块数据的数据。子块的每个数据集与单个主字地址相关。 DRAM具有用于在感测锁存器和存储器之间选择数据传输模式的额外数据存储器。通过存储，DRAM能够将具有不同行地址的多个数据集同时传送到感测锁存器。

2. 发明授权

US5566118A Dynamic semiconductor memory device with sense amplifiers as cache memories 失效
标题翻译：具有读出放大器的动态半导体存储器件作为高速缓冲存储器
公开(公告)号：US5566118A
公开(公告)日：1996-10-15
申请号：US549076
申请日：1995-10-27
申请人： Tamio Shimizu
发明人： Tamio Shimizu
IPC分类号： G11C11/403 , G06F12/08 , G11C11/401 , G11C11/406 , G11C8/00
CPC分类号： G11C11/406
摘要： In a dynamic DRAM device including a plurality of memory cell blocks associated with sense amplifier arrays as cache memories, and registers for storing addresses of the memory cell blocks to indicate the contents of the sense amplifiers, a refresh address for a self-refresh mode is sequentially generated to perform a refresh operation upon the memoty cell blocks. When the refresh address coincides with a predetermined value, data of the memory cell blocks is read by using an address of one of the registers and is restored in a corresponding sense amplifer array.
摘要翻译：在包括与作为高速缓冲存储器的读出放大器阵列相关联的多个存储单元块的动态DRAM装置中，以及用于存储存储单元块的地址以指示读出放大器的内容的寄存器，用于自刷新模式的刷新地址是顺序地生成以对记忆单元块执行刷新操作。当刷新地址与预定值一致时，通过使用其中一个寄存器的地址来读取存储单元块的数据，并在对应的读出放大器阵列中被还原。

3. 发明授权

US5644535A Semiconductor device having plural memories which synchronously generate acess allow signals 失效
标题翻译：具有同步产生摄像允许信号的多个存储器的半导体器件
公开(公告)号：US5644535A
公开(公告)日：1997-07-01
申请号：US626240
申请日：1996-03-29
申请人： Tamio Shimizu
发明人： Tamio Shimizu
IPC分类号： G11C11/401 , G06F12/08 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22
摘要： A memory access request signal is generated with activation of three different signals, i.e., memory select signal, operating mode signal and operating input signal. When only the memory select signal and operating mode signal are activated, internal operation is not executed, and only an operating mode for determining access allow signal generation timing is determined. The access allow signal is generated at the same timing as the execution of the operating mode.
摘要翻译：存储器访问请求信号通过激活三个不同的信号，即存储器选择信号，工作模式信号和操作输入信号产生。当只有存储器选择信号和操作模式信号被激活时，不执行内部操作，并且仅确定用于确定访问的操作模式允许信号产生定时。在与执行操作模式相同的定时产生访问允许信号。

4. 发明授权

US5353866A Heat transfer fins and heat exchanger 失效
标题翻译：换热片和热交换器
公开(公告)号：US5353866A
公开(公告)日：1994-10-11
申请号：US038190
申请日：1993-03-29
申请人： Hironobu Ueda , Toshio Hatada , Yoshifumi Kunugi , Tomihisa Oouchi , Sigeo Sugimoto , Tamio Shimizu , Kyoji Kohno
发明人： Hironobu Ueda , Toshio Hatada , Yoshifumi Kunugi , Tomihisa Oouchi , Sigeo Sugimoto , Tamio Shimizu , Kyoji Kohno
IPC分类号： F25B15/00 , F28F1/32 , F28D9/00
CPC分类号： F28F1/325 , F25B15/008
摘要： Louver segments of a heat transfer fin each have a longitudinal central portion disposed at the center of the louver segment in a direction crossing the flow of a fluid and longitudinal end portions each disposed on either side of the longitudinal central portion and sectioned into parts. Each louver segment has a configuration such that an area of the longitudinal central portion projected in the direction of the flow of the fluid is larger than an area of each of the longitudinal end portions projected in the direction of the flow of the fluid, with respect to the same width of the passage of the fluid.
摘要翻译：传热翅片的百叶窗段具有纵向中心部分，该纵向中心部分沿着与流体纵向端部交叉的方向设置在百叶窗部分的中心，纵向端部分别设置在纵向中心部分的任一侧并且被分成多个部分。每个百叶窗段具有这样的构造，使得沿着流体的流动方向突出的纵向中心部分的面积大于沿着流体的流动方向突出的每个纵向端部的面积，相对于到流体通道的相同宽度。

5. 发明申请

US20100127673A1 Power feed system and voltage stabilization method 审中-公开
标题翻译：供电系统和电压稳定方法
公开(公告)号：US20100127673A1
公开(公告)日：2010-05-27
申请号：US12656190
申请日：2010-01-20
申请人： Yasuhiro Iino , Tamio Shimizu , Takahiro Miyazaki , Toshifumi Washio
发明人： Yasuhiro Iino , Tamio Shimizu , Takahiro Miyazaki , Toshifumi Washio
IPC分类号： G05F1/563
CPC分类号： H02M3/335 , H02M2001/0045 , H02M2001/007
摘要： A voltage stabilizing circuit is provided between an insulated converter and a non-insulated converter. When an input voltage Vin from the insulated converter rises, a base current Ib is caused to flow into a transistor via a capacitor, thereby causing a collector current Ic that is hfe times larger than the base current Ib to flow into a collector of the transistor. As a result, a capacitance C of the capacitor is caused to produce approximately the same effect as that produced in a case where a capacitor whose capacitance is equivalent to a value obtained by multiplying the capacitance by the current amplification factor hfe of the transistor is inserted between a power supply line and a ground.
摘要翻译：在绝缘转换器和非绝缘转换器之间提供稳压电路。当来自绝缘转换器的输入电压Vin升高时，使基极电流Ib经由电容器流入晶体管，从而使得比基极电流Ib大h倍的集电极电流Ic流入晶体管的集电极。结果，使电容器的电容C产生大致相同的效果，即将电容等于通过将电容乘以晶体管的电流放大系数hfe而获得的值的电容器插入在电源线和地之间。

6. 发明申请

US20050185431A1 DC/DC converter 审中-公开
标题翻译： DC / DC转换器
公开(公告)号：US20050185431A1
公开(公告)日：2005-08-25
申请号：US11042351
申请日：2005-01-26
申请人： Tamio Shimizu , Taku Nobiki
发明人： Tamio Shimizu , Taku Nobiki
IPC分类号： H02M3/28 , H02M3/335
CPC分类号： H02M3/33561 , H02M3/33523
摘要： A tertiary coil is provided in a DC/DC converter. An electric current is generated in the tertiary coil due to on an alternating-current voltage produced in the tertiary coil. An electrical current supplying circuit supplies the electric current generated in the tertiary coil to a load when supplementary power must be supplied to the load.
摘要翻译：在DC / DC转换器中提供三级线圈。由于在三次线圈中产生的交流电压，在三次线圈中产生电流。当向负载提供补充电力时，电流供给电路将在三次线圈中产生的电流提供给负载。

7. 发明授权

US4941329A Double effect air-cooled absorption refrigerating machine 失效
标题翻译：双效风冷吸收式制冷机
公开(公告)号：US4941329A
公开(公告)日：1990-07-17
申请号：US316941
申请日：1989-02-28
申请人： Kouji Imura , Tomihisa Ohuchi , Kyoji Kohno , Tamio Shimizu , Michihiko Aizawa
发明人： Kouji Imura , Tomihisa Ohuchi , Kyoji Kohno , Tamio Shimizu , Michihiko Aizawa
IPC分类号： F25B15/00
CPC分类号： F25B15/008 , Y02B30/62
摘要： Fans are disposed on an upper wall face out of the upper wall face, a lower wall face and side wall faces which constitute an outside frame of a machine body. An air-cooled absorber is disposed on two adjacent wall faces. An air-cooled condenser is disposed on one wall face of the remaining side wall faces. A main apparatus comprising such as an evaporator, a high-temperature regenerator, a low-temperature regenerator, a solution heat exchanger and pipes for connecting operatively the apparatuses together is disposed on an inner portion of the machine body so as to be surrounded by the air-cooled absorber and the air-cooled condenser. Thus, a noise generated from the refrigerating machine is reduced.
摘要翻译：风扇设置在构成机体外框架的上壁面，下壁面和侧壁面的上壁面上。空气冷却吸收器设置在两个相邻的壁面上。在其余侧壁面的一个壁面上设置有风冷式冷凝器。包括诸如蒸发器，高温再生器，低温再生器，溶液热交换器和用于将设备一起连接的管道的主要装置设置在机体的内部，以便被风冷吸收器和空气冷却冷凝器。因此，降低了从制冷机产生的噪音。

8. 发明授权

US5590081A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5590081A
公开(公告)日：1996-12-31
申请号：US546982
申请日：1995-10-23
申请人： Tamio Shimizu
发明人： Tamio Shimizu
IPC分类号： G11C11/409 , G11C7/12 , G11C11/401 , G11C11/406 , G11C11/4076 , G11C11/4094 , G11C8/00
CPC分类号： G11C11/4076 , G11C11/4094 , G11C7/12
摘要： A dynamic semiconductor memory device includes a timing signal generator for controlling a precharge operation such that the predetermined precharge operation is completed, during a memory refresh cycle, for a sense amplifier and bit lines corresponding thereto for the next memory access. The memory device using the sense amplifier as cache keeping means is capable of increasing the memory access speed immediately after a memory refresh operation.
摘要翻译：动态半导体存储器件包括用于控制预充电操作的定时信号发生器，使得在存储器刷新周期期间完成预定的预充电操作，用于读出放大器和对应于其的下一个存储器访问的位线。使用读出放大器作为高速缓存保存装置的存储装置能够在存储器刷新操作之后立即增加存储器访问速度。

9. 发明授权

US5301162A Semiconductor random access memory device having shared sense amplifiers serving as a cache memory 失效
标题翻译：具有用作高速缓冲存储器的共享读出放大器的半导体随机存取存储器件
公开(公告)号：US5301162A
公开(公告)日：1994-04-05
申请号：US35238
申请日：1993-03-23
申请人： Tamio Shimizu
发明人： Tamio Shimizu
IPC分类号： G11C11/409 , G06F12/08 , G11C7/06 , G11C8/12 , G11C11/401 , G11C15/04
CPC分类号： G11C8/12 , G06F12/0893 , G11C7/06
摘要： A random access memory device has memory cell blocks, row address decoders respectively associated with the memory cell blocks, sense amplifier circuit arrays each shared between two of the memory cell blocks, and a column selecting unit for transferring a data bit from one of the sense amplifier circuit arrays to an output data buffer circuit, a flag generating unit for producing flag signals indicative of memory cell blocks supplying the data bits presently stored in the sense amplifier circuit arrays, and an address discriminating unit operative to examine block and row addresses supplied from the outside thereof to see whether or not an accessed data bit has been already stored in the sense amplifier circuit arrays, thereby allowing the shared sense amplifier circuit arrays to serve as a cache memory.
摘要翻译：随机存取存储器件具有存储单元块，分别与存储单元块相关联的行地址解码器，在两个存储单元块之间共享的读出放大器电路阵列和用于从该感测中的一个传送数据位的列选择单元放大器电路阵列到输出数据缓冲器电路，标志产生单元，用于产生指示提供当前存储在读出放大器电路阵列中的数据位的存储单元块的标志信号;以及地址鉴别单元，用于检查从在外部，以查看访问数据位是否已经存储在读出放大器电路阵列中，从而允许共享读出放大器电路阵列用作高速缓冲存储器。

10. 发明授权

US5706244A Semiconductor memory device having shared sense amplifier arrays individually controlled for cache storage 失效
标题翻译：具有单独控制用于高速缓存存储的共享读出放大器阵列的半导体存储器件
公开(公告)号：US5706244A
公开(公告)日：1998-01-06
申请号：US549943
申请日：1995-10-30
申请人： Tamio Shimizu
发明人： Tamio Shimizu
IPC分类号： G11C11/401 , G06F12/08 , G11C11/4091 , G11C7/00
CPC分类号： G11C11/4091 , G06F12/0893
摘要： A semiconductor dynamic random access memory device has shared sense amplifier units used for not only magnification of data bits but also serving as a cache storage, and a cache system incorporated in the semiconductor dynamic random access memory device individually controls the sense amplifier units to determine whether to allow an access to the selected sense amplifier unit, thereby enhancing the hit ratio.
摘要翻译：半导体动态随机存取存储器件具有不仅用于数据位放大而且用作高速缓冲存储器的共享读出放大器单元，并且包含在半导体动态随机存取存储器件中的高速缓存系统分别控制读出放大器单元以确定是否以允许访问所选择的读出放大器单元，从而提高命中率。

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