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1. 发明授权

US5760457A Bipolar transistor circuit element having base ballasting resistor 失效
标题翻译：具有基极镇流电阻的双极晶体管电路元件
公开(公告)号：US5760457A
公开(公告)日：1998-06-02
申请号：US806396
申请日：1997-02-26
申请人： Shigeru Mitsui , Takuji Sonoda , Teruyuki Shimura , Saburo Takamiya
发明人： Shigeru Mitsui , Takuji Sonoda , Teruyuki Shimura , Saburo Takamiya
IPC分类号： H01L21/331 , H01L21/8222 , H01L27/06 , H01L29/08 , H01L29/205 , H01L29/73 , H01L29/737 , H01L29/00 , H01L31/0328
CPC分类号： H01L29/0817 , H01L27/0658 , H01L29/7304 , H01L29/7371
摘要： A bipolar transistor circuit element includes a semiconductor substrate; successively disposed on the substrate, a base layer, an emitter layer, and a collector layer; a bipolar transistor formed from parts of the collector, base, and emitter layers and including a base electrode electrically connected to the base layer and a base electrode pad for making an external connection to the base layer; a base ballasting resistor formed from a part of the base layer isolated from the bipolar transistor and electrically connecting the base electrode to the base electrode pad; and a base parallel capacitor connected in parallel with the base ballasting resistor wherein the base parallel capacitor includes part of the base input pad, a dielectric film disposed on part of the base electrode pad, and a second electrode disposed on the dielectric layer opposite the base electrode pad and electrically connected to the emitter electrode of the bipolar transistor. The base ballasting resistor has a high resistance relative to an emitter ballasting reactor so that it can be easily mass produced with good uniformity and yield.
摘要翻译：双极晶体管电路元件包括半导体衬底; 依次设置在基板上，基底层，发射极层和集电极层; 由集电极，基极和发射极层的部分形成的双极性晶体管，并且包括电连接到基极层的基极和用于与基极层进行外部连接的基极焊盘; 由与所述双极型晶体管隔离的所述基极层的一部分形成的基极保护电阻器，并且将所述基极电极与所述基极电极焊盘电连接; 以及与所述基极镇流电阻并联连接的基极并联电容器，其中所述基极并联电容器包括所述基极输入焊盘的一部分，设置在所述基极电极焊盘的一部分上的电介质膜，以及设置在与所述基极相对的所述电介质层上的第二电极电极焊盘并电连接到双极晶体管的发射极。碱性镇流电阻器相对于发射极压载反应器具有高电阻，使得其可以容易地以均匀性和产率良好地批量生产。

2. 发明授权

US06861906B2 High-frequency semiconductor device 有权
标题翻译：高频半导体器件
公开(公告)号：US06861906B2
公开(公告)日：2005-03-01
申请号：US10204446
申请日：2001-05-11
申请人： Kazutomi Mori , Shintaro Shinjo , Kousei Maemura , Teruyuki Shimura , Kazuhiko Nakahara , Tadashi Takagi
发明人： Kazutomi Mori , Shintaro Shinjo , Kousei Maemura , Teruyuki Shimura , Kazuhiko Nakahara , Tadashi Takagi
IPC分类号： H01L27/06 , H03F3/19 , H03F3/21 , H03F3/68
CPC分类号： H01L27/0605 , H03F3/19 , H03F3/211 , H03F2203/21178
摘要： A high-frequency semiconductor device according to the present invention achieves improvements in degradation of noise characteristics and a reduction in gain, and an improvement in reduction in power efficiency while suppressing a concentration of a current to multifinger HBTs. In the multifinger HBTs constituting a first stage and an output stage of an amplifier 10, basic HBTs 14 that constitute the multifinger HBT 12 corresponding to the first stage, are each made up of an HBT 14a and an emitter resistor 14b connected to the corresponding emitter of the HBT 14a, whereas basic HBTs 18 that constitute the multifinger HBT 16 corresponding to the output stage, are each comprised of an HBT 18a and a base resistor 18c connected to the corresponding base of the HBT 18a. The high-frequency semiconductor device according to the present invention is useful as a high output power amplifier used in satellite communications, ground microwave communications, mobile communications, etc.
摘要翻译：根据本发明的高频半导体器件实现了噪声特性的降低和增益的降低的改善，并且在抑制电流到多焦HBT的浓度的同时，提高了功率效率的降低。在构成放大器10的第一级和输出级的多画面HBT中，构成对应于第一级的多画面HBT 12的基本HBT 14分别由连接到相应发射极的HBT 14a和发射极电阻14b组成而构成与输出级相对应的多功能HBT16的基本HBT 18分别由连接到HBT 18a的相应基座的HBT 18a和基极电阻18c组成。根据本发明的高频半导体器件可用作卫星通信，地面微波通信，移动通信等中使用的高输出功率放大器。

3. 发明授权

US5973543A Bias circuit for bipolar transistor 失效
标题翻译：双极晶体管的偏置电路
公开(公告)号：US5973543A
公开(公告)日：1999-10-26
申请号：US825220
申请日：1997-03-27
申请人： Teruyuki Shimura
发明人： Teruyuki Shimura
IPC分类号： H03F3/20 , G05F3/22 , H03F3/04 , G05F1/10
CPC分类号： G05F3/22
摘要： A bias circuit for a bipolar transistor includes a constant voltage source connected to a base electrode of the bipolar transistor; and a resistor connected in series between the constant voltage source and the base electrode of the bipolar transistor. By selecting an appropriate resistance for this resistor, the bias point moves due to a change in the voltage drop across the resistor. The change occurs because the base current flowing through the resistor changes, whereby the operating class of the transistor changes, resulting in a high efficiency at a desired output power.
摘要翻译：用于双极晶体管的偏置电路包括连接到双极晶体管的基极的恒压源; 以及串联连接在双极晶体管的恒定电压源和基极之间的电阻器。通过为该电阻选择合适的电阻，偏置点由于电阻上的电压降的变化而移动。发生这种变化是因为流过电阻的基极电流发生变化，晶体管的工作类别发生变化，导致所需输出功率的效率高。

4. 发明授权

US4977100A Method of fabricating a MESFET 失效
标题翻译：制造MESFET的方法
公开(公告)号：US4977100A
公开(公告)日：1990-12-11
申请号：US417288
申请日：1989-10-05
申请人： Teruyuki Shimura
发明人： Teruyuki Shimura
IPC分类号： H01L29/812 , H01L21/285 , H01L21/338 , H01L29/417 , H01L29/423
CPC分类号： H01L29/66878 , H01L21/28587 , H01L29/42316
摘要： A method of producing a MESFET which includes forming a refractory metal gate structure on an active layer formed in or on a semiconductor substrate. Source and drain regions optionally with extensions, are formed adjacent the gate structure. An insulating film is deposited over the partly formed structure to form a film portion on the semiconductor substrate which is separated from further film portions formed over the source and drain regions. A flattening resist is deposited over the insulating film and etched to expose only the film portion on the gate structure, while the gate structure itself and the resist protects the film portions on the source and drain regions. The film portion over the gate structure can thus be removed without damage to the gate structure or the remainder of the insulating film. The process produces with increased yield and more consistent properties in that the danger of attacking the refractory metal gate structure during operations succeeding its formation is significantly reduced.
摘要翻译：一种MESFET的制造方法，其特征在于，在形成于半导体基板中的有源层上形成难熔金属栅极结构。源极和漏极区域可选地具有延伸部分，邻近栅极结构形成。在部分形成的结构上沉积绝缘膜，以在半导体衬底上形成薄膜部分，其与形成在源区和漏区上的其它膜部分分离。平坦化抗蚀剂沉积在绝缘膜上并被蚀刻以仅暴露栅极结构上的膜部分，而栅极结构本身和抗蚀剂保护源极和漏极区域上的膜部分。因此，能够去除栅极结构上的膜部分，而不会损坏栅极结构或绝缘膜的其余部分。该方法产生具有增加的产量和更一致的性质，因为在其形成过程中的操作期间攻击难熔金属栅极结构的危险性显着降低。

5. 发明授权

US6081003A Heterojunction bipolar transistor with ballast resistor 失效
标题翻译：具有镇流电阻的异质结双极晶体管
公开(公告)号：US6081003A
公开(公告)日：2000-06-27
申请号：US985364
申请日：1997-12-04
申请人： Shinichi Miyakuni , Teruyuki Shimura
发明人： Shinichi Miyakuni , Teruyuki Shimura
IPC分类号： H01L29/73 , H01L21/302 , H01L21/3065 , H01L21/331 , H01L29/08 , H01L29/205 , H01L29/737 , H01L31/072 , H01L31/0328 , H01L31/0336 , H01L31/109
CPC分类号： H01L29/66318 , H01L29/0817 , H01L29/7371
摘要： A heterojunction bipolar transistor is provided with a ballast resistor layer in an emitter layer which prevents the current amplification factor .beta. from decreasing. The n-GaAs carrier supply layer having a specified carrier concentration is formed between the ballast resistor layer and the n-AlGaAs layer.
摘要翻译：异质结双极晶体管在发射极层中设置有镇流电阻层，防止电流放大因子β降低。在镇流电阻层和n-AlGaAs层之间形成具有规定载流子浓度的n-GaAs载流子供给层。

6. 发明授权

US5192700A Method of making field effect transistor 失效
标题翻译：制作场效应晶体管的方法
公开(公告)号：US5192700A
公开(公告)日：1993-03-09
申请号：US828374
申请日：1992-01-30
申请人： Teruyuki Shimura
发明人： Teruyuki Shimura
IPC分类号： H01L21/265 , H01L21/337 , H01L21/338 , H01L21/76 , H01L27/095 , H01L29/778 , H01L29/80 , H01L29/808 , H01L29/812
CPC分类号： H01L29/66924 , H01L21/7605 , H01L29/802 , H01L29/808
摘要： A field effect transistor including a semi-insulating semiconductor substrate, a first conductivity type semiconductor layer disposed on the substrate and forming a heterojunction with the substrate, second conductivity type spaced apart source and drain regions extending through the layer into the substrate, a metallic gate disposed on the layer between the source and drain regions, and a second conductivity type channel disposed in the substrate extending between the source and drain regions and forming a pn heterojunction with the layer for reducing leakage current from the channel to the gate. The second conductivity type channel is produced by ion implantation, and the implantation conditions are controlled as a mechanism for controllably establishing a threshold voltage for the field effect transistor.
摘要翻译：一种场效应晶体管，包括半绝缘半导体衬底，设置在衬底上并与衬底形成异质结的第一导电类型半导体层，延伸穿过衬底的第二导电类型间隔开的源极和漏极区，金属栅极设置在源极和漏极区域之间的层上，以及第二导电类型沟道，设置在衬底中，在源极和漏极区域之间延伸，并且与该层形成pn异质结，以减少从沟道到栅极的泄漏电流。通过离子注入产生第二导电类型沟道，并且将注入条件作为用于可控地建立场效应晶体管的阈值电压的机制来控制。

7. 发明授权

US5073812A Heterojunction bipolar transistor 失效
标题翻译：异相双极晶体管
公开(公告)号：US5073812A
公开(公告)日：1991-12-17
申请号：US481619
申请日：1990-02-20
申请人： Teruyuki Shimura
发明人： Teruyuki Shimura
IPC分类号： H01L29/73 , H01L21/033 , H01L21/331 , H01L29/205 , H01L29/737
CPC分类号： H01L29/66318 , H01L21/033
摘要： A semiconductor device includes an n.sup.+ type InGaAs layer at a surface of the device, a refractory metal emitter electrode making ohmic contact to the n.sup.+ layer without alloying, and an externally accessible base region produced in the neighborhood of the emitter electrode by a diffusion using the emitter electrode and an insulating side wall film as a diffusion mask.
摘要翻译：半导体器件在器件的表面包括n +型InGaAs层，难熔金属发射极电极，其在没有合金化的情况下与n +层形成欧姆接触，并且通过扩散使用在发射极附近产生的外部可接近的基极区域发射电极和绝缘侧壁膜作为扩散掩模。

8. 发明授权

US4967254A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4967254A
公开(公告)日：1990-10-30
申请号：US217292
申请日：1988-07-11
申请人： Teruyuki Shimura
发明人： Teruyuki Shimura
IPC分类号： H01L29/08
CPC分类号： H01L29/0804 , Y10S148/111
摘要： A semiconductor device includes a collector layer comprising a first conductivity type semiconductor layer, a base layer comprising a second conductivity type semiconductor layer produced on the collector layer, an emitter layer comprising a first conductivity type semiconductor layer produced on the base layer, a contact layer comprising an undoped semiconductor layer produced on the emitter layer, second conductivity type first implantation regions produced at regions each consisting of the contact layer, the emitter layer, and the base layer, so as to leave a central region therebetween, base electrodes produced on the first implantation regions, a first conductivity type second implantation region produced by implanting impurities from the surface of the contact layer extending into the emitter layer, in a region between the first implantation regions, and an emitter electrode produced on the second implantation region. Or, a semiconductor device includes an emitter layer comprising undoped semiconductor layer and a first conductivity type second implantation region produced by implanting impurities from the surface of the undoped semiconductor layer extending into the base layer, at a region between the first implantation regions.
摘要翻译：半导体器件包括：集电极层，包括第一导电类型半导体层;基底层，包括在集电极层上制造的第二导电类型半导体层;发射极层，包括在基底层上制造的第一导电型半导体层;接触层包括在发射极层上产生的未掺杂的半导体层，在由接触层，发射极层和基极层组成的区域处产生的第二导电类型的第一注入区域，以在其间留下中心区域，在第一注入区域，通过从在第一注入区域之间的区域中延伸到发射极层的接触层的表面注入杂质而产生的第一导电类型的第二注入区域和在第二注入区域上产生的发射极。或者，半导体器件包括发射极层，其包括未掺杂半导体层和通过在第一注入区域之间的区域处从未掺杂的半导体层的表面注入杂质而产生的第一导电类型的第二注入区域。

9. 发明授权

US07145397B2 Output overvoltage protection circuit for power amplifier 有权
标题翻译：功率放大器输出过压保护电路
公开(公告)号：US07145397B2
公开(公告)日：2006-12-05
申请号：US10889059
申请日：2004-07-13
申请人： Kazuya Yamamoto , Teruyuki Shimura , Tomoyuki Asada , Satoshi Suzuki
发明人： Kazuya Yamamoto , Teruyuki Shimura , Tomoyuki Asada , Satoshi Suzuki
IPC分类号： H03F1/52
CPC分类号： H03F1/52
摘要： Disclosed is an output overvoltage protection circuit for a power amplifier having a plurality of stages, which comprises a monitor circuit for monitoring an output overvoltage of an output transistor in the final stage of the power amplifier and allowing a current to flow therethrough in response to the monitored output overvoltage, and a current mirror circuit for supplying a current proportional to the current from the monitor circuit in such a manner that the base bias of the first-stage transistor of the power amplifier is reduced in response to the current supplied from the current mirror circuit, to reduce the output of the final-stage output transistor.
摘要翻译：公开了一种用于具有多级的功率放大器的输出过电压保护电路，其包括监视电路，用于监视功率放大器的最后级中的输出晶体管的输出过电压，并且允许电流响应于监控的输出过电压，以及电流镜电路，用于提供与来自监视器电路的电流成比例的电流，使得功率放大器的第一级晶体管的基极偏置响应于从电流提供的电流而减小镜像电路，以减少最终级输出晶体管的输出。

10. 发明授权

US5889434A Microwave power amplifier 失效
标题翻译：微波功率放大器
公开(公告)号：US5889434A
公开(公告)日：1999-03-30
申请号：US888543
申请日：1997-07-07
申请人： Teruyuki Shimura , Takeshi Miura , Tadashi Takagi
发明人： Teruyuki Shimura , Takeshi Miura , Tadashi Takagi
IPC分类号： H03F3/60 , H03F1/32 , H03F3/195 , H03F3/191
CPC分类号： H03F1/3241
摘要： A microwave power amplifier having n stages (n is an integer of at least two), which uses bipolar transistors as amplifying elements. Grounded electrodes, bias applying methods, and bias values of the bipolar transistors of the respective stages are set so that phase rotations of output powers of bipolar transistors of m stages (m is an integer of 1.ltoreq.m.ltoreq.n-1) among the n stages are canceled by phase rotation of at least one of the other bipolar transistors of the (n-m) stages. Therefore, the total phase rotation of the power amplifier can be neutralized, resulting in a microwave power amplifier having excellent distortion characteristics.
摘要翻译：具有n级（n为至少2的整数）的微波功率放大器，其使用双极晶体管作为放大元件。设置接地电极，偏置施加方法和各级双极晶体管的偏置值，使得m级双极型晶体管的输出功率的相位旋转（m为1≤n≤n-1的整数）通过（nm）级的至少一个其他双极晶体管的相位旋转而被抵消。因此，可以中和功率放大器的总相位旋转，导致具有优异失真特性的微波功率放大器。

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