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1. 发明授权

US08139402B2 Magnetic memory device 有权
标题翻译：磁存储器件
公开(公告)号：US08139402B2
公开(公告)日：2012-03-20
申请号：US12349542
申请日：2009-01-07
申请人： Hiroaki Tanizaki , Shuichi Ueno , Yasumitsu Murai , Takaharu Tsuji
发明人： Hiroaki Tanizaki , Shuichi Ueno , Yasumitsu Murai , Takaharu Tsuji
IPC分类号： G11C11/14
CPC分类号： H01L27/228 , H01L43/08
摘要： A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed. The magnetic memory device includes the strap wiring, the local via, and a magnetic recording element (TMR element). The TMR element includes a fixed layer and the recording layer. The planar shape of the recording layer is asymmetric with respect to the direction of the easy magnetization axis of the recording layer and is symmetric with respect to the axis of symmetry perpendicular to the easy magnetization axis. The contoured portion of the recording layer on the side closer to the center of area of the recording layer is opposed to the local via formation side.
摘要翻译：提供了一种磁存储器件，其中即使具有不对称形状和局部通孔的记录层形成在具有允许的足够距离的带布线之间，也可以抑制磁存储器件的尺寸的增加。磁存储器件包括带状布线，本地通孔和磁记录元件（TMR元件）。 TMR元件包括固定层和记录层。记录层的平面形状相对于记录层的易磁化轴的方向是不对称的，并且相对于垂直于易磁化轴的对称轴对称。在记录层的更靠近记录层的中心的一侧的记录层的轮廓部分与局部通孔形成侧相对。

2. 发明申请

US20100034015A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100034015A1
公开(公告)日：2010-02-11
申请号：US12473832
申请日：2009-05-28
申请人： Takaharu TSUJI
发明人： Takaharu TSUJI
IPC分类号： G11C11/00 , G11C8/08 , G11C11/416 , G11C8/00
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1673
摘要： The invention provides a semiconductor device having a lower probability of erroneous inversion of data signal. The MRAM disclosed herein comprises (m+1)×(n+1) memory cells arranged in (m+1) rows and (n+1) columns, digit lines respectively provided in the rows, and bit lines respectively provided in the columns. A magnetizing current Im caused to flow through a digit line in a selected row makes all memory cells half-selected in the row, while a writing current is caused to flow through (n+1) bit lines to write data signals of (n+1) bits into the (n+1) memory cells, the direction of the writing current depending on the logic of each of these data signals. Thus, erroneous inversion of data signal due to a magnetic field in a digit line is avoided.
摘要翻译：本发明提供了具有较低的数据信号反转概率的半导体器件。本文公开的MRAM包括排列在（m + 1）行和（n + 1）列中的行（m + 1）x（n + 1）个存储单元，分别设置在行中的数字行，以及分别设置在列中的位线。磁化电流Im导致选定行中的数字线流动，使得所有存储单元在行中被半选择，同时使写入电流流过（n + 1）位线以写入（n + 1）位数据信号， 1）位到（n + 1）个存储单元中，写入电流的方向取决于每个这些数据信号的逻辑。因此，避免了由于数字线中的磁场引起的数据信号的错误反转。

3. 发明授权

US07486547B2 Semiconductor integrated circuit device and magnetic memory device capable of maintaining data integrity 有权
标题翻译：能够保持数据完整性的半导体集成电路器件和磁存储器件
公开(公告)号：US07486547B2
公开(公告)日：2009-02-03
申请号：US11889029
申请日：2007-08-08
申请人： Takaharu Tsuji
发明人： Takaharu Tsuji
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： Magnetic memory devices integrated together with a logic circuit on a common semiconductor chip are arranged to have layouts mirror-symmetrical (mirror inversion) with respect to an axis parallel to a magnetization-hard axis of a magneto-resistance element of a magnetic memory cell in the magnetic memory device. The logic circuit is arranged between the magnetic memory devices. The magnetic memory device capable accurately of maintaining integrity in logical level between write data and read data is achieved.
摘要翻译：与公共半导体芯片上的逻辑电路集成在一起的磁存储器件被布置成具有相对于与磁存储单元的磁阻元件的磁化 - 硬轴平行的轴的镜对称（镜像反转）的布局磁存储器件。逻辑电路布置在磁存储器件之间。实现了能够准确地保持写入数据和读取数据之间的逻辑电平的完整性的磁存储器件。

4. 发明授权

US07272032B2 Semiconductor integrated circuit device and magnetic memory device capable of maintaining data integrity 有权
公开(公告)号：US07272032B2
公开(公告)日：2007-09-18
申请号：US11062496
申请日：2005-02-23
申请人： Takaharu Tsuji
发明人： Takaharu Tsuji
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： Magnetic memory devices integrated together with a logic circuit on a common semiconductor chip are arranged to have layouts mirror-symmetrical (mirror inversion) with respect to an axis parallel to a magnetization-hard axis of a magneto-resistance element of a magnetic memory cell in the magnetic memory device. The logic circuit is arranged between the magnetic memory devices. The magnetic memory device capable accurately of maintaining integrity in logical level between write data and read data is achieved.

5. 发明申请

US20070133265A1 Semiconductor integrated circuit device with a plurality of memory cells storing data 失效
标题翻译：具有存储数据的多个存储单元的半导体集成电路器件
公开(公告)号：US20070133265A1
公开(公告)日：2007-06-14
申请号：US11605290
申请日：2006-11-29
申请人： Takaharu Tsuji
发明人： Takaharu Tsuji
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A semiconductor integrated circuit device includes a plurality of memory cells storing data; a write current line arranged near the memory cells or electrically connected to the memory cells; a first constant current generating circuit providing an output current having a temperature dependence; a second constant current generating circuit providing an output current having a temperature dependence different from that of the output current of the first constant current generating circuit; a mixing circuit mixing the output currents of the constant current generating circuits together to provide a composite current at a variable mixing rate; and a write current electrically connected to the write current line and writing data into the memory cell by passing a write circuit through the write current line based on the composite current provided by the mixing circuit.
摘要翻译：半导体集成电路装置包括存储数据的多个存储单元; 写入电流线，布置在存储器单元附近或电连接到存储器单元; 提供具有温度依赖性的输出电流的第一恒定电流产生电路; 提供具有不同于所述第一恒定电流产生电路的输出电流的温度依赖性的输出电流的第二恒定电流产生电路; 混合电路将恒定电流产生电路的输出电流混合在一起以提供可变混合速率的复合电流; 以及写入电流，其电连接到写入电流线，并且基于由混合电路提供的复合电流，通过使写入电路通过写入电流线来将数据写入存储单元。

6. 发明授权

US06791876B2 Thin-film magnetic memory device suppressing parasitic capacitance applied to data line or the like 失效
标题翻译：抑制施加到数据线等的寄生电容的薄膜磁存储器件
公开(公告)号：US06791876B2
公开(公告)日：2004-09-14
申请号：US10397352
申请日：2003-03-27
申请人： Hiroaki Tanizaki , Takaharu Tsuji , Hideto Hidaka
发明人： Hiroaki Tanizaki , Takaharu Tsuji , Hideto Hidaka
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： A plurality of bit lines are divided into a plurality of groups each including Y (Y: integer of at least two) bit lines. Y data read data lines passing a data read current therethrough in data reading are provided along with Y connection control parts electrically coupling Y bit lines and the Y read data lines with each other every group. Therefore, the connection control parts electrically connected with the Y read data lines are uniformly divided so that parasitic capacitance applied to the read data lines following electrical connection with the connection control parts can be suppressed. Therefore, the time for charging the read data lines to a prescribed voltage level can be reduced for executing high-speed data reading.
摘要翻译：多个位线被分成多个组，每组包括Y（Y：至少两个的整数）位线。在数据读取中通过数据读取电流的Y数据读取数据线与Y个连接控制部分一起被提供，Y个连接控制部分将Y位线和Y个读取数据线彼此电组合。因此，与Y读取数据线电连接的连接控制部分被均匀地分割，从而能够抑制与连接控制部件电连接之后的读取数据线路的寄生电容。因此，为了执行高速数据读取，可以减少将读取数据线充电到规定电压电平的时间。

7. 发明授权

US06778434B2 Magnetic random access memory device with a reduced number of interconnections for selection of address 失效
标题翻译：具有减少数量的互连的磁性随机存取存储器件用于选择地址
公开(公告)号：US06778434B2
公开(公告)日：2004-08-17
申请号：US10461429
申请日：2003-06-16
申请人： Takaharu Tsuji
发明人： Takaharu Tsuji
IPC分类号： G11C1115
CPC分类号： G11C8/14 , G11C11/16
摘要： Each memory cell row is associated with access transistors having their source regions electrically connected together by an n+ diffusion node extending in the direction of the row. The n+ diffusion node is connected to a main word line set to have the low level (a ground voltage) in selecting a corresponding memory cell row. When the main word line is set low, responsively in a data read operation a selected row's word line is set high and in a data write operation a selected row's digit line is set high.
摘要翻译：每个存储单元行与存取晶体管相关联，其存取晶体管的源极区通过在行方向上延伸的n +扩散节点电连接在一起。在选择对应的存储单元行时，n +扩散节点连接到设置为具有低电平（地电压）的主字线。当主字线设置为低电平时，响应于数据读取操作，所选行的字线被设置为高，并且在数据写入操作中，所选行的数字线被设置为高。

8. 发明授权

US06618317B1 Write system architecture of magnetic memory array divided into a plurality of memory blocks 失效
标题翻译：将磁存储器阵列的系统架构写入多个存储器块
公开(公告)号：US06618317B1
公开(公告)日：2003-09-09
申请号：US10331492
申请日：2002-12-31
申请人： Takaharu Tsuji , Tsukasa Ooishi
发明人： Takaharu Tsuji , Tsukasa Ooishi
IPC分类号： G11C1115
CPC分类号： G11C11/16
摘要： During data write, a first driver electrically connects a fist shared node to one of first and second voltages in accordance with write data. A second driver electrically connects a second shared node to the other voltage. A plurality of first switch circuits for electrically connecting one end sides of bit lines to the first shared node, respectively, and a plurality of second switch circuits for electrically connecting the other end sides to the second shared node, respectively, are provided. In accordance with a column select result, the first and second switch circuit for the corresponding bit line are turned on. Therefore, it is possible to execute a data write operation without providing a driver for each bit line.
摘要翻译：在数据写入期间，第一驱动器根据写入数据将第一共享节点电连接到第一和第二电压之一。第二驱动器将第二共享节点电连接到另一个电压。提供了用于将位线的一端侧分别电连接到第一共享节点的多个第一开关电路和用于将另一端侧分别电连接到第二共享节点的多个第二开关电路。根据列选择结果，相应位线的第一和第二开关电路导通。因此，可以在不为每个位线提供驱动器的情况下执行数据写入操作。

9. 发明授权

US06584022B2 Semiconductor memory device with simultaneous data line selection and shift redundancy selection 有权
标题翻译：具有同时数据线选择和移位冗余选择的半导体存储器件
公开(公告)号：US06584022B2
公开(公告)日：2003-06-24
申请号：US09971697
申请日：2001-10-09
申请人： Takaharu Tsuji
发明人： Takaharu Tsuji
IPC分类号： G11C2900
CPC分类号： G11C29/848
摘要： The semiconductor memory device includes a memory cell array, a normal data line pair, a redundant data line pair and a data line switch circuit. The data line switch circuit includes an IO shift decoder decoding the column address and the position information related to a defective data line, and an IO select unit shifting the connection between a data input/output pin and a data line while replacing the defective data line according to the decoded result. High speed data transfer is realized by carrying out simultaneously data line selection and redundancy selection according to the column address.
摘要翻译：半导体存储器件包括存储单元阵列，普通数据线对，冗余数据线对和数据线切换电路。数据线切换电路包括对列地址和与有缺陷数据线有关的位置信息进行解码的IO移位译码器，以及在选择缺陷数据线替换数据输入/输出引脚与数据线之间的连接的IO选择单元根据解码结果。根据列地址同时进行数据线选择和冗余选择，实现高速数据传输。

10. 发明授权

US06373315B1 Signal potential conversion circuit 有权
公开(公告)号：US06373315B1
公开(公告)日：2002-04-16
申请号：US09793997
申请日：2001-02-28
申请人： Takaharu Tsuji , Shigeki Tomishima , Tsukasa Ooishi
发明人： Takaharu Tsuji , Shigeki Tomishima , Tsukasa Ooishi
IPC分类号： H03L500
摘要： In a signal potential conversion circuit of a DRAM, a first P channel MOS transistor for charging a first node is connected in parallel with a second P channel MOS transistor and the second P channel MOS transistor is turned on in a pulse manner in response to a rising edge of an input signal. Further, the first P channel MOS transistor has its current drive ability defined to be approximately one-tenth of that of an N channel MOS transistor for discharging the first node. Accordingly, each of the first node and a second node can be charged and discharged quickly to enable conversion of a signal potential to be accomplished speedily.

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