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1. 发明授权

US06384674B2 Semiconductor device having hierarchical power supply line structure improved in operating speed 失效
标题翻译：具有分级供电线路结构的半导体装置提高了运行速度
公开(公告)号：US06384674B2
公开(公告)日：2002-05-07
申请号：US09353349
申请日：1999-07-15
申请人： Hiroaki Tanizaki , Tsukasa Ooishi , Shigeki Tomishima , Masatoshi Ishikawa , Hideto Hidaka , Takaharu Tsuji
发明人： Hiroaki Tanizaki , Tsukasa Ooishi , Shigeki Tomishima , Masatoshi Ishikawa , Hideto Hidaka , Takaharu Tsuji
IPC分类号： G05F110
CPC分类号： G11C5/063 , G11C11/4074 , G11C11/4097 , H02J1/06
摘要： Provided is a power supply-to-power supply capacitance cell including a first capacitor connected between a sub power supply line and a sub ground line, a second capacitor connected between a main power supply line and the sub ground line, and a third capacitor connected between the sub power supply line and a main ground line. Thus, a voltage drop of the sub power supply line can be reduced in current consumption of an internal circuit, so that an operation of the internal circuit is stabilized and the operating speed thereof is improved.
摘要翻译：提供了一种电源电源电容单元，包括连接在副电源线和副地线之间的第一电容器，连接在主电源线和副地线之间的第二电容器和连接在主电源线和副地线之间的第三电容器在副电源线和主接地线之间。因此，可以降低内部电路的电流消耗中的副电源线的电压降，使得内部电路的动作稳定，其运转速度提高。

2. 发明授权

US07436699B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07436699B2
公开(公告)日：2008-10-14
申请号：US11645610
申请日：2006-12-27
申请人： Hiroaki Tanizaki , Takaharu Tsuji , Yasumitsu Murai , Hideto Hidaka
发明人： Hiroaki Tanizaki , Takaharu Tsuji , Yasumitsu Murai , Hideto Hidaka
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/5607 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0078 , G11C2213/31 , G11C2213/79
摘要： Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.
摘要翻译：自旋注入磁存储单元的源极线与字线平行地布置，用于一次执行数据多位读写。在写入操作中，源极线电位以预定的顺序改变，使得共同连接到多个选择的存储器单元的源极线被设置为仅在操作序列的每个阶段中在一个方向上传递电流。对于数据写入序列，根据写入数据顺序地使电流流过存储器单元，或者存储单元在写入之前具有设置为初始电阻状态的电阻状态，然后根据写入数据快速变为状态可以在磁存储器中实现写入，而不增加存储单元布局区域。

3. 发明授权

US06791876B2 Thin-film magnetic memory device suppressing parasitic capacitance applied to data line or the like 失效
标题翻译：抑制施加到数据线等的寄生电容的薄膜磁存储器件
公开(公告)号：US06791876B2
公开(公告)日：2004-09-14
申请号：US10397352
申请日：2003-03-27
申请人： Hiroaki Tanizaki , Takaharu Tsuji , Hideto Hidaka
发明人： Hiroaki Tanizaki , Takaharu Tsuji , Hideto Hidaka
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： A plurality of bit lines are divided into a plurality of groups each including Y (Y: integer of at least two) bit lines. Y data read data lines passing a data read current therethrough in data reading are provided along with Y connection control parts electrically coupling Y bit lines and the Y read data lines with each other every group. Therefore, the connection control parts electrically connected with the Y read data lines are uniformly divided so that parasitic capacitance applied to the read data lines following electrical connection with the connection control parts can be suppressed. Therefore, the time for charging the read data lines to a prescribed voltage level can be reduced for executing high-speed data reading.
摘要翻译：多个位线被分成多个组，每组包括Y（Y：至少两个的整数）位线。在数据读取中通过数据读取电流的Y数据读取数据线与Y个连接控制部分一起被提供，Y个连接控制部分将Y位线和Y个读取数据线彼此电组合。因此，与Y读取数据线电连接的连接控制部分被均匀地分割，从而能够抑制与连接控制部件电连接之后的读取数据线路的寄生电容。因此，为了执行高速数据读取，可以减少将读取数据线充电到规定电压电平的时间。

4. 发明申请

US20070159870A1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070159870A1
公开(公告)日：2007-07-12
申请号：US11645610
申请日：2006-12-27
申请人： Hiroaki Tanizaki , Takaharu Tsuji , Yasumitsu Murai , Hideto Hidaka
发明人： Hiroaki Tanizaki , Takaharu Tsuji , Yasumitsu Murai , Hideto Hidaka
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/5607 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0078 , G11C2213/31 , G11C2213/79
摘要： Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.
摘要翻译：自旋注入磁存储单元的源极线与字线平行地布置，用于一次执行数据多位读写。在写入操作中，源极线电位以预定的顺序改变，使得共同连接到多个选择的存储器单元的源极线被设置为仅在操作序列的每个阶段中在一个方向上传递电流。对于数据写入序列，根据写入数据顺序地使电流流过存储器单元，或者存储单元在写入之前具有设置为初始电阻状态的电阻状态，然后根据写入数据快速变为状态可以在磁存储器中实现写入，而不增加存储单元布局区域。

5. 发明授权

US07233537B2 Thin film magnetic memory device provided with a dummy cell for data read reference 失效
标题翻译：具有用于数据读取参考的虚拟单元的薄膜磁存储器件
公开(公告)号：US07233537B2
公开(公告)日：2007-06-19
申请号：US10260397
申请日：2002-10-01
申请人： Hiroaki Tanizaki , Hideto Hidaka , Takaharu Tsuji , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Hideto Hidaka , Takaharu Tsuji , Tsukasa Ooishi
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/14 , G11C11/4087 , G11C11/4091 , G11C11/4099 , G11C2207/2281
摘要： Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.
摘要翻译：正常存储单元和虚设单元连续地布置在存储器阵列中。在数据读取操作中，第一和第二数据线分别连接到所选择的存储单元和虚拟单元，并且被提供有差分放大器的工作电流。在第一和第二数据线的通过电流之间提供对应于从电压产生电路施加的第一和第二偏移控制电压之间的电压差的偏移，并且通过虚设单元的参考电流被设置为两种之间的水平的电平对应于通过所选存储单元的数据读取电流的存储数据。

6. 发明授权

US06885235B2 Semiconductor integrated circuit device with internal power supply potential generation circuit 失效
标题翻译：具有内部电源电位生成电路的半导体集成电路器件
公开(公告)号：US06885235B2
公开(公告)日：2005-04-26
申请号：US10095080
申请日：2002-03-12
申请人： Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
发明人： Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C29/06 , G05F3/04
CPC分类号： G11C5/147
摘要： An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.
摘要翻译：内部电源电位产生电路包括连接到内部电源节点的过充电防止电路。过充电防止电路包括输出由内部电源电位确定的待确定信号的电路，放大要确定的信号之间的电位差和作为输出到节点的参考电位的差分放大电路作为信号表示应该绘制电流，并且响应于指示应当绘制电流的信号，从内部电源节点抽出电流的电流绘制电路。因此，感兴趣的半导体集成电路器件可以提供稳定的内部电源电位。

7. 发明授权

US06466509B1 Semiconductor memory device having a column select line transmitting a column select signal 失效
标题翻译：具有发送列选择信号的列选择线的半导体存储器件
公开(公告)号：US06466509B1
公开(公告)日：2002-10-15
申请号：US10050131
申请日：2002-01-18
申请人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C11/4087 , G11C2207/104
摘要： First and second memory banks are provided with M memory blocks each having first and second memory regions, M representing an even number of no less than two, and (M+1) sense amplifier bands arranged on opposite sides of each memory block, and have first and second select lines arranged therefor to select the first and second memory regions, respectively, the first select line being connected to an odd-numbered sense amplifier band of the first memory bank and an even-numbered sense amplifier band of the second memory bank, the second select line being connected to an even-numbered sense amplifier band of the first memory bank and an odd-numbered sense amplifier band of the second memory bank.
摘要翻译：第一和第二存储体设置有M个存储块，每个存储块具有第一和第二存储区域，M表示偶数个不少于两个，以及（M + 1）个读出放大器频带，其布置在每个存储块的相对侧上，并具有第一选择线和第二选择线分别用于选择第一和第二存储区，第一选择线连接到第一存储体的奇数读出放大器带和第二存储体的偶数读出放大器带第二选择线连接到第一存储体的偶数读出放大器带和第二存储体的奇数读出放大器带。

8. 发明授权

US06411560B1 Semiconductor memory device capable of reducing leakage current flowing into substrate 失效
标题翻译：能够减少流入基板的漏电流的半导体存储器件
公开(公告)号：US06411560B1
公开(公告)日：2002-06-25
申请号：US09987277
申请日：2001-11-14
申请人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
IPC分类号： G11C514
CPC分类号： G11C7/1096 , G11C5/146 , G11C5/147 , G11C7/1078 , G11C7/22 , G11C8/10 , G11C11/4074
摘要： A first power supply voltage is supplied to a power supply node of a sense amplifier. A bit line driver outputs a column select signal composed of a second power supply voltage to the gate terminals of N channel MOS transistors of a GIO line gate circuit. When input/output data is [1], a third power supply voltage lower than the first power supply voltage is supplied onto a global data line. In this case, with a threshold voltage of N channel MOS transistors used, a relation is established: second power supply voltage≦third power supply voltage+threshold voltage. As a result, a leakage current can be reduced in a semiconductor memory device driven by plural power supply voltages with respective different voltage levels.
摘要翻译：第一电源电压被提供给读出放大器的电源节点。位线驱动器将由第二电源电压组成的列选择信号输出到GIO线路电路的N沟道MOS晶体管的栅极端子。当输入/输出数据为[1]时，低于第一电源电压的第三电源电压被提供给全局数据线。在这种情况下，利用所使用的N沟道MOS晶体管的阈值电压，建立关系：第二电源电压<=第三电源电压+阈值电压。结果，在由具有不同电压电平的多个电源电压驱动的半导体存储器件中，可以减小泄漏电流。

9. 发明授权

US06603685B2 Semiconductor integrated circuit device capable of ensuring reliability of transistor driving high voltage 失效
标题翻译：半导体集成电路器件能够确保晶体管驱动高电压的可靠性
公开(公告)号：US06603685B2
公开(公告)日：2003-08-05
申请号：US09778261
申请日：2001-02-08
申请人： Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
发明人： Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
IPC分类号： G11C700
CPC分类号： G11C5/147 , G11C5/145 , G11C11/4074 , G11C11/4087
摘要： A driving circuit includes a voltage converting circuit receiving a block selection signal and converting to a signal of a boosted potential level, and first and second N channel MOS transistors connected in series between the boosted potential and the ground potential. The gate of the first transistor receives the boosted potential, and a potential level at a connection node between the first and second transistors is provided as a signal BLI (i, 0).
摘要翻译：驱动电路包括接收块选择信号并转换为升压电位信号的电压转换电路，以及串联在升压电位和地电位之间的第一和第N N沟道MOS晶体管。第一晶体管的栅极接收升压电位，并且第一和第二晶体管之间的连接节点处的电位电平被提供为信号BLI（i，0）。

10. 发明授权

US06842366B2 Thin film magnetic memory device executing self-reference type data read 失效
标题翻译：执行自参考型数据读取的薄膜磁存储器件
公开(公告)号：US06842366B2
公开(公告)日：2005-01-11
申请号：US10383570
申请日：2003-03-10
申请人： Hiroaki Tanizaki , Tsukasa Ooishi , Hideto Hidaka
发明人： Hiroaki Tanizaki , Tsukasa Ooishi , Hideto Hidaka
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/14
CPC分类号： G11C11/15 , G11C11/1673
摘要： In one data read operation, data read for reading stored data before and after a predetermined data write magnetic field is applied to a selected memory cell, respectively, is executed, and the data read is executed in accordance with comparison of voltage levels corresponding to the data read operations before and after application of the predetermined data write magnetic field. In addition, data read operations before and after the application of a data write magnetic field are executed using read modify write. It is thereby possible to avoid an influence of an offset or the like resulting from manufacturing irregularities in respective circuits forming a data read path, to improve efficiency of the data read operation with accuracy and to execute a high rate data read operation.
摘要翻译：在一个数据读取操作中，执行用于将预定数据写入磁场之前和之后的存储数据读取的数据分别施加到所选择的存储单元，并且根据与数据读取操作在应用预定数据写入磁场之前和之后。另外，数据写入磁场的应用前后的数据读取操作是使用读修改写进行的。从而可以避免在形成数据读取路径的各个电路中由制造不规则引起的偏移等的影响，从而精确地提高数据读取操作的效率并执行高速数据读取操作。

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