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1. 发明授权

US06868029B2 Semiconductor device with reduced current consumption in standby state 有权
标题翻译：半导体器件在待机状态下具有降低的电流消耗
公开(公告)号：US06868029B2
公开(公告)日：2005-03-15
申请号：US10607259
申请日：2003-06-27
申请人： Tsukasa Ooishi , Takaharu Tsuji , Masatoshi Ishikawa , Hideto Hidaka , Hiroshi Kato
发明人： Tsukasa Ooishi , Takaharu Tsuji , Masatoshi Ishikawa , Hideto Hidaka , Hiroshi Kato
IPC分类号： G11C11/403 , G06F1/26 , G11C5/14 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/406 , G11C11/407 , H01L27/148 , H03K19/00 , H03K19/096
CPC分类号： G11C7/1006 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4074 , G11C2207/2227 , G11C2211/4067
摘要： A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.
摘要翻译：逻辑部分向DRAM部分输出指示存储区域的起始地址和结束地址，其中存储的数据在转换到具有降低的电流消耗的掉电模式之前存在。在断电模式中，刷新控制单元保存起始地址和结束地址，并且仅在需要刷新的区域中控制要进行数据刷新。逻辑部分的电源在掉电模式下被设置为断开状态，因此半导体器件可以在保持数据的同时消耗电流。

2. 发明授权

US06597617B2 Semiconductor device with reduced current consumption in standby state 有权
公开(公告)号：US06597617B2
公开(公告)日：2003-07-22
申请号：US10167437
申请日：2002-06-13
申请人： Tsukasa Ooishi , Takaharu Tsuji , Masatoshi Ishikawa , Hideto Hidaka , Hiroshi Kato
发明人： Tsukasa Ooishi , Takaharu Tsuji , Masatoshi Ishikawa , Hideto Hidaka , Hiroshi Kato
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4074 , G11C2207/2227 , G11C2211/4067
摘要： A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

3. 发明授权

US06384674B2 Semiconductor device having hierarchical power supply line structure improved in operating speed 失效
标题翻译：具有分级供电线路结构的半导体装置提高了运行速度
公开(公告)号：US06384674B2
公开(公告)日：2002-05-07
申请号：US09353349
申请日：1999-07-15
申请人： Hiroaki Tanizaki , Tsukasa Ooishi , Shigeki Tomishima , Masatoshi Ishikawa , Hideto Hidaka , Takaharu Tsuji
发明人： Hiroaki Tanizaki , Tsukasa Ooishi , Shigeki Tomishima , Masatoshi Ishikawa , Hideto Hidaka , Takaharu Tsuji
IPC分类号： G05F110
CPC分类号： G11C5/063 , G11C11/4074 , G11C11/4097 , H02J1/06
摘要： Provided is a power supply-to-power supply capacitance cell including a first capacitor connected between a sub power supply line and a sub ground line, a second capacitor connected between a main power supply line and the sub ground line, and a third capacitor connected between the sub power supply line and a main ground line. Thus, a voltage drop of the sub power supply line can be reduced in current consumption of an internal circuit, so that an operation of the internal circuit is stabilized and the operating speed thereof is improved.
摘要翻译：提供了一种电源电源电容单元，包括连接在副电源线和副地线之间的第一电容器，连接在主电源线和副地线之间的第二电容器和连接在主电源线和副地线之间的第三电容器在副电源线和主接地线之间。因此，可以降低内部电路的电流消耗中的副电源线的电压降，使得内部电路的动作稳定，其运转速度提高。

4. 发明授权

US06618317B1 Write system architecture of magnetic memory array divided into a plurality of memory blocks 失效
标题翻译：将磁存储器阵列的系统架构写入多个存储器块
公开(公告)号：US06618317B1
公开(公告)日：2003-09-09
申请号：US10331492
申请日：2002-12-31
申请人： Takaharu Tsuji , Tsukasa Ooishi
发明人： Takaharu Tsuji , Tsukasa Ooishi
IPC分类号： G11C1115
CPC分类号： G11C11/16
摘要： During data write, a first driver electrically connects a fist shared node to one of first and second voltages in accordance with write data. A second driver electrically connects a second shared node to the other voltage. A plurality of first switch circuits for electrically connecting one end sides of bit lines to the first shared node, respectively, and a plurality of second switch circuits for electrically connecting the other end sides to the second shared node, respectively, are provided. In accordance with a column select result, the first and second switch circuit for the corresponding bit line are turned on. Therefore, it is possible to execute a data write operation without providing a driver for each bit line.
摘要翻译：在数据写入期间，第一驱动器根据写入数据将第一共享节点电连接到第一和第二电压之一。第二驱动器将第二共享节点电连接到另一个电压。提供了用于将位线的一端侧分别电连接到第一共享节点的多个第一开关电路和用于将另一端侧分别电连接到第二共享节点的多个第二开关电路。根据列选择结果，相应位线的第一和第二开关电路导通。因此，可以在不为每个位线提供驱动器的情况下执行数据写入操作。

5. 发明授权

US06373315B1 Signal potential conversion circuit 有权
公开(公告)号：US06373315B1
公开(公告)日：2002-04-16
申请号：US09793997
申请日：2001-02-28
申请人： Takaharu Tsuji , Shigeki Tomishima , Tsukasa Ooishi
发明人： Takaharu Tsuji , Shigeki Tomishima , Tsukasa Ooishi
IPC分类号： H03L500
摘要： In a signal potential conversion circuit of a DRAM, a first P channel MOS transistor for charging a first node is connected in parallel with a second P channel MOS transistor and the second P channel MOS transistor is turned on in a pulse manner in response to a rising edge of an input signal. Further, the first P channel MOS transistor has its current drive ability defined to be approximately one-tenth of that of an N channel MOS transistor for discharging the first node. Accordingly, each of the first node and a second node can be charged and discharged quickly to enable conversion of a signal potential to be accomplished speedily.

6. 发明授权

US06414894B2 Semiconductor device with reduced current consumption in standby state 失效
标题翻译：半导体器件在待机状态下具有降低的电流消耗
公开(公告)号：US06414894B2
公开(公告)日：2002-07-02
申请号：US09778062
申请日：2001-02-07
申请人： Tsukasa Ooishi , Takaharu Tsuji , Masatoshi Ishikawa , Hideto Hidaka , Hiroshi Kato
发明人： Tsukasa Ooishi , Takaharu Tsuji , Masatoshi Ishikawa , Hideto Hidaka , Hiroshi Kato
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4074 , G11C2207/2227 , G11C2211/4067
摘要： A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.
摘要翻译：逻辑部分向DRAM部分输出指示存储区域的起始地址和结束地址，其中存储的数据在转换到具有降低的电流消耗的掉电模式之前存在。在断电模式中，刷新控制单元保存起始地址和结束地址，并且仅在需要刷新的区域中控制要进行数据刷新。逻辑部分的电源在掉电模式下被设置为断开状态，因此半导体器件可以在保持数据的同时消耗电流。

7. 发明授权

US6058053A Semiconductor memory device capable of high speed operation and including redundant cells 有权
标题翻译：半导体存储器件能够高速运行并且包括冗余单元
公开(公告)号：US6058053A
公开(公告)日：2000-05-02
申请号：US195212
申请日：1998-11-18
申请人： Takaharu Tsuji , Tsukasa Ooishi , Hiroshi Kato , Shigeki Tomishima , Hiroki Shimano
发明人： Takaharu Tsuji , Tsukasa Ooishi , Hiroshi Kato , Shigeki Tomishima , Hiroki Shimano
IPC分类号： G11C29/04 , G11C29/00 , G11C7/00
CPC分类号： G11C29/84 , G11C29/844
摘要： In the semiconductor memory device, independent from redundancy determination by a redundancy determining circuit, a word line activating signal (subdecode signal) for setting a word line in a normal block corresponding to a decoded address signal, is activated. A WL driver includes a driver portion for selecting a word line in the normal block, and a driver portion for selecting a spare word line in a redundant block. When redundancy is not to be used as a result of redundancy determination by the redundancy determining circuit, activated subdecode signal is inactivated. If redundancy is to be used as a result of redundancy determination, a corresponding word line is set to the selected state, using the activated subdecode signal. Thus a semiconductor memory device in which substitution can be done at high speed with high efficiency is provided.
摘要翻译：在半导体存储器件中，独立于由冗余确定电路进行的冗余确定，激活用于设置与解码的地址信号对应的正常块中的字线的字线激活信号（子代码信号）。 WL驱动器包括用于选择正常块中的字线的驱动器部分和用于在冗余块中选择备用字线的驱动器部分。作为由冗余确定电路的冗余确定的结果不使用冗余时，激活的子代码信号被去激活。如果作为冗余确定的结果使用冗余，则使用激活的子代码信号将对应的字线设置为所选择的状态。因此，提供了可以以高效率高效率地进行替换的半导体存储器件。

8. 发明授权

US07233537B2 Thin film magnetic memory device provided with a dummy cell for data read reference 失效
标题翻译：具有用于数据读取参考的虚拟单元的薄膜磁存储器件
公开(公告)号：US07233537B2
公开(公告)日：2007-06-19
申请号：US10260397
申请日：2002-10-01
申请人： Hiroaki Tanizaki , Hideto Hidaka , Takaharu Tsuji , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Hideto Hidaka , Takaharu Tsuji , Tsukasa Ooishi
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/14 , G11C11/4087 , G11C11/4091 , G11C11/4099 , G11C2207/2281
摘要： Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.
摘要翻译：正常存储单元和虚设单元连续地布置在存储器阵列中。在数据读取操作中，第一和第二数据线分别连接到所选择的存储单元和虚拟单元，并且被提供有差分放大器的工作电流。在第一和第二数据线的通过电流之间提供对应于从电压产生电路施加的第一和第二偏移控制电压之间的电压差的偏移，并且通过虚设单元的参考电流被设置为两种之间的水平的电平对应于通过所选存储单元的数据读取电流的存储数据。

9. 发明授权

US06885235B2 Semiconductor integrated circuit device with internal power supply potential generation circuit 失效
标题翻译：具有内部电源电位生成电路的半导体集成电路器件
公开(公告)号：US06885235B2
公开(公告)日：2005-04-26
申请号：US10095080
申请日：2002-03-12
申请人： Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
发明人： Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C29/06 , G05F3/04
CPC分类号： G11C5/147
摘要： An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.
摘要翻译：内部电源电位产生电路包括连接到内部电源节点的过充电防止电路。过充电防止电路包括输出由内部电源电位确定的待确定信号的电路，放大要确定的信号之间的电位差和作为输出到节点的参考电位的差分放大电路作为信号表示应该绘制电流，并且响应于指示应当绘制电流的信号，从内部电源节点抽出电流的电流绘制电路。因此，感兴趣的半导体集成电路器件可以提供稳定的内部电源电位。

10. 发明授权

US06856537B2 Thin film magnetic memory device having dummy cell 失效
标题翻译：具有虚拟电池的薄膜磁存储器件
公开(公告)号：US06856537B2
公开(公告)日：2005-02-15
申请号：US10299776
申请日：2002-11-20
申请人： Hiroaki Tanizaki , Takaharu Tsuji , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Takaharu Tsuji , Tsukasa Ooishi
IPC分类号： G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/00 , G11C11/14
CPC分类号： G11C11/16
摘要： A dummy cell has a plurality of dummy magneto-resistance elements which have the same characteristic as a magneto-resistance element, which characteristic changes corresponding to a voltage applied to the opposite ends. In addition, a voltage applied to opposite ends of each dummy magneto-resistance element is made smaller than a voltage applied to opposite ends of a magneto-resistance element of a memory cell. With this, the dummy cell is designed so as to have an intermediate electric resistance between first and second electric resistances.
摘要翻译：虚拟单元具有多个具有与磁阻元件相同的特性的虚拟磁阻元件，其特性随施加到相对端的电压而变化。此外，施加到每个虚拟磁阻元件的相对端的电压小于施加到存储单元的磁阻元件的相对端的电压。由此，虚设电池被设计成在第一和第二电阻之间具有中间电阻。

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