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1. 发明授权

US5144158A ECL latch circuit having a noise resistance circuit in only one feedback path 失效
标题翻译： ECL锁存电路在仅一个反馈路径中具有噪声电阻电路
公开(公告)号：US5144158A
公开(公告)日：1992-09-01
申请号：US511958
申请日：1990-04-17
申请人： Yasunori Kanai , Kazumasa Nawata , Mitsuhisa Shimizu , Hiroki Yada , Taichi Saitoh , Toshiaki Sakai
发明人： Yasunori Kanai , Kazumasa Nawata , Mitsuhisa Shimizu , Hiroki Yada , Taichi Saitoh , Toshiaki Sakai
IPC分类号： H03K3/013 , H03K3/037
CPC分类号： H03K3/013 , H03K3/0375
摘要： A latch circuit including at least three gate circuits, and a noise resistance circuit. A first gate circuit (3, 4, 11, 16) receives a data signal (DT) and a clock signal (CLK). A second gate circuit (1, 7, 13, 17) is connected to an output of the first gate circuit. A third gate circuit (2, 5, 12 18) receives a first inverted clock signal (CLK) at an input terminal. A second input terminal of the third gate circuit is connected to an output of the second gate circuit and is a first output terminal is connected to an input terminal of the second gate circuit, so that a feedback line is formed between the second and third gate circuits. The noise resistance circuit (8, 9, 20, 21) has at least a signal delay element in the feedback line. The noise resistance circuit may include a filter circuit. The noise resistance circuit may also include an amplifier circuit.
摘要翻译：包括至少三个门电路的锁存电路和一个噪声电阻电路。第一门电路（3,4,11,16）接收数据信号（DT）和时钟信号（CLK）。第二门电路（1,7,13,17）连接到第一门电路的输出端。第三门电路（2,5,12,18）在输入端接收第一反相时钟信号（＆amp; upbar＆C）。第三门电路的第二输入端连接到第二门电路的输出，并且第一输出端连接到第二门电路的输入端，从而在第二和第三门之间形成反馈线电路。噪声电阻电路（8,9,20,21）在反馈线中至少具有信号延迟元件。噪声电阻电路可以包括滤波电路。噪声电阻电路还可以包括放大器电路。

2. 发明授权

US5436573A High-speed semiconductor integrated circuit device with reduced delay in gate-to-gate wiring 失效
标题翻译：高速半导体集成电路器件，栅极到栅极布线的延迟减小
公开(公告)号：US5436573A
公开(公告)日：1995-07-25
申请号：US113828
申请日：1993-08-31
申请人： Rokutarou Ogawa , Taichi Saitoh , Tosiaki Sakai
发明人： Rokutarou Ogawa , Taichi Saitoh , Tosiaki Sakai
IPC分类号： H01L27/118 , H01L21/82 , H01L21/822 , H01L23/522 , H01L27/04 , H03K19/013 , H03K19/00 , H01L25/00
CPC分类号： H03K19/013 , H01L23/5222 , H01L2924/0002
摘要： A semiconductor integrated circuit device has a first wire for transmitting a first signal and a second wire adjacent to the first wire, for transmitting a second signal having the stronger probability of having an opposite phase to that of the first signal. A space between the first and second wires is wider than a standard wiring space, to reduce a delay in the operation speed of the device due to wiring capacitance produced between the first and second wires.
摘要翻译：半导体集成电路器件具有用于传输第一信号的第一线和与第一线相邻的第二线，用于发送具有与第一信号相反的相位的较强概率的第二信号。第一和第二导线之间的空间比标准布线空间宽，以减少由于在第一和第二导线之间产生的布线电容而导致的器件的操作速度的延迟。

3. 发明授权

US5118973A Emitter coupled logic circuit having independent input transistors 失效
标题翻译：具有独立输入晶体管的发射极耦合逻辑电路
公开(公告)号：US5118973A
公开(公告)日：1992-06-02
申请号：US570857
申请日：1990-08-22
申请人： Toshiaki Sakai , Taichi Saitoh
发明人： Toshiaki Sakai , Taichi Saitoh
IPC分类号： H01L27/082 , H01L21/8222 , H03K17/0412 , H03K17/66 , H03K19/013 , H03K19/086
CPC分类号： H03K17/04126 , H03K17/666 , H03K19/0136 , H03K19/086
摘要： An improved emitter coupled logic circuit suitable for high speed logic operation independent of capacitive load. With previous circuits as the load to be driven become heavier, the capacitive load required a longer time for discharge and the output signal was dulled, resulting in adverse effect on the logic operation when the output changed to a low level from a high level. A pulse has also been previously applied to a pull-down transistor connected between the output and a power source through a capacitor from an inverted phase output to actively discharge the capacitive load. However, when the capacitor is connected to the output it hinders the switching speed of a current switch. In the present invention, a transistor is provided an input circuit and a pulse is applied to a pull-down transistor from the transistor. As a result, an extra capacitive element is not connected to the output end, but a pulse is applied to the pull-down transistor. Accordingly, even if the capacitive load becomes heavier, the speed of the circuit is not harmed.
摘要翻译：一种改进的发射极耦合逻辑电路，适用于独立于电容负载的高速逻辑运算。随着驱动负载变得越来越重，电容负载需要较长的放电时间，输出信号变钝，当输出从高电平变为低电平时，对逻辑运算产生不利影响。先前已经将脉冲施加到通过来自反相输出的电容器连接在输出和电源之间的下拉晶体管，以主动放电容性负载。然而，当电容器连接到输出时，它阻碍了电流开关的开关速度。在本发明中，晶体管被提供有输入电路，并且脉冲从晶体管施加到下拉晶体管。结果，额外的电容元件不连接到输出端，但是脉冲被施加到下拉晶体管。因此，即使容性负载变重，电路的速度也不会受到损害。

4. 发明授权

US4678942A Emitter coupled logic circuit with high drivability for capacitive load 失效
标题翻译：用于容性负载的发射极耦合逻辑电路具有高驱动能力
公开(公告)号：US4678942A
公开(公告)日：1987-07-07
申请号：US779356
申请日：1985-09-23
申请人： Yasunori Kanai , Taichi Saitoh
发明人： Yasunori Kanai , Taichi Saitoh
IPC分类号： H03K19/00 , H03K19/01 , H03K19/013 , H03K19/0175 , H03K19/018 , H03K19/086
CPC分类号： H03K19/0136 , H03K19/001 , H03K19/086
摘要： An ECL (Emitter Coupled Logic) circuit is provided which has an increased ability to drive a large capacitive load or to drive a large fan-out circuit, wherein the power consumption per gate is reduced. The output circuit of the ECL circuit is provided with an emitter follower transistor which has the current therethrough detected by a detecting transistor. A current control transistor is provided to quickly charge the load capacitance under the control of the detecting transistor, and thus, the voltage drop of the output signal is improved. One of the emitter follower transistor and the current transistor are always cut off when the other is in a conductive state, and therefore, the current running through the circuit is reduced.
摘要翻译：提供了一种ECL（发射极耦合逻辑）电路，其具有增加的驱动大容性负载或驱动大扇出电路的能力，其中每个门的功耗降低。 ECL电路的输出电路设置有具有由检测晶体管检测的电流的射极跟随器晶体管。提供电流控制晶体管，以在检测晶体管的控制下对负载电容进行快速充电，从而提高输出信号的电压降。当另一个处于导通状态时，射极跟随器晶体管和电流晶体管中的一个总是截止，因此，流过电路的电流减小。

5. 发明授权

US5216296A Logic circuit having sharper falling edge transition 失效
标题翻译：逻辑电路具有更尖锐的下降沿转换
公开(公告)号：US5216296A
公开(公告)日：1993-06-01
申请号：US896929
申请日：1992-06-11
申请人： Hiroyuki Tsunoi , Kazumasa Nawata , Toshiaki Sakai , Hiroki Yada , Hisayosi Ooba , Takayuki Tsuru , Satoru Sudo , Taichi Saitoh
发明人： Hiroyuki Tsunoi , Kazumasa Nawata , Toshiaki Sakai , Hiroki Yada , Hisayosi Ooba , Takayuki Tsuru , Satoru Sudo , Taichi Saitoh
IPC分类号： H03K19/013 , H03K19/086
CPC分类号： H03K19/086 , H03K19/0136
摘要： A logic circuit in which first and second transistors are connected in series between high and low potential power sources with the middle point of the series connection used as the output terminal; A same- and inverse-phase signal generating unit is provided connected between the high and low potential power sources in parallel with the first and second transistors for generating same- and inverse-phase signals based on the single input signal output from the logic circuit. A transient signal generating unit is provided for generating transient large current signals at the rise time of the inverse-phase signals and generating transient cut-off signals at the fall time of the inverse-phase signals. The series connected first transistor is driven and controlled based on the regular-phase signals, while the second transistor is driven and controlled based on the transient large current signal and transient cut-off signal, thus producing an inverse-phase output by a simple circuit construction.
摘要翻译：一种逻辑电路，其中第一和第二晶体管串联连接在高电平和低电位电源之间，串联中点用作输出端; 提供相同和反相信号产生单元，其连接在与第一和第二晶体管并联的高电平和低电位电源之间，用于基于从逻辑电路输出的单个输入信号产生相位和反相信号。提供了一个瞬态信号发生单元，用于在反相信号的上升时间产生瞬时大电流信号，并在反相信号的下降时间产生瞬态截止信号。基于正相信号驱动和控制串联的第一晶体管，而基于瞬态大电流信号和瞬态截止信号驱动和控制第二晶体管，从而通过简单电路产生反相输出施工。

6. 发明授权

US4975544A Connecting structure for connecting conductors in an electronic apparatus 失效
标题翻译：电子设备连接导体的连接结构
公开(公告)号：US4975544A
公开(公告)日：1990-12-04
申请号：US323757
申请日：1989-03-15
申请人： Nobuyuki Tanaka , Taichi Saitoh , Akio Kiso , Hideo Tokuda , Tetsuya Nakajima , Minoru Takagi
发明人： Nobuyuki Tanaka , Taichi Saitoh , Akio Kiso , Hideo Tokuda , Tetsuya Nakajima , Minoru Takagi
IPC分类号： H01L23/482
CPC分类号： H01L23/4824 , H01L2924/0002
摘要： A connecting structure for connecting conductors used for wiring in a semiconductor device comprises a first conductor provided on a part of the semiconductor device for passing the flow of electrons, an insulator provided on the first conductor and formed with a contact hole, and a second conductor provided on the insulator for passing the flow of electrons, in which the second conductor is provided so as to sandwich the insulator together with a part of the first conductor. The first and second conductors are contacted to each other across the insulator at the contact hole so that the electrons flow through the contact hole. The contact hole extends in a general direction of a flow of electrons passing therethrough and has a stepped shape in which a width measured perpendicularly to the general direction of the flow of electrons increases stepwise towards the general direction of the flow of electrons.

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