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1. 发明申请

US20110248734A1 ELECTRONIC DEVICE TEST APPARATUS 有权
标题翻译：电子装置测试装置
公开(公告)号：US20110248734A1
公开(公告)日：2011-10-13
申请号：US13018726
申请日：2011-02-01
申请人： Yasuhide TAKEDA , Hiroyuki NAGAI , Yoji OGINO , Tatsuya YAMADA
发明人： Yasuhide TAKEDA , Hiroyuki NAGAI , Yoji OGINO , Tatsuya YAMADA
IPC分类号： G01R31/20 , G01R31/26
CPC分类号： G01R31/2893 , G01R1/0483 , G01R31/2867 , G01R31/2874
摘要： An electronic device test apparatus which can optimize throughput and costs is provided.An electronic device test apparatus 1 comprises: a test cell cluster 10 having cell groups 11A to 11H each of which has a plurality of test cells 20; and a conveyor apparatus 30 supplying test carriers to a plurality of the test cells 20, and each of the test cell 20 has: contactors 215; a flow path 221 connected to a vacuum pump 25 and reducing pressure in a recess 211 of a pocket 21 so as to bring external terminals 73 and the contactors 215 into contact; and a test circuit for running a test on an electronic circuit formed into a die 90.
摘要翻译：提供了可以优化生产量和成本的电子设备测试装置。电子设备测试装置1包括：具有单元组11A至11H的测试单元簇10，每个单元组具有多个测试单元20; 以及向多个测试单元20提供测试载体的传送装置30，并且每个测试单元20具有：接触器215; 连接到真空泵25的流路221，并且减小袋21的凹部211中的压力，使外部端子73和接触器215接触; 以及用于在形成为模具90的电子电路上运行测试的测试电路。

2. 发明申请

US20110161763A1 TEST APPARATUS AND SYNCHRONIZATION METHOD 有权
标题翻译：测试装置和同步方法
公开(公告)号：US20110161763A1
公开(公告)日：2011-06-30
申请号：US13029065
申请日：2011-02-16
申请人： Tatsuya YAMADA
发明人： Tatsuya YAMADA
IPC分类号： G01R31/3183 , G06F11/22
CPC分类号： G01R31/31726 , G01R31/31922
摘要： Provided is a test apparatus that tests a device under test, comprising (i) a master domain that includes a master period signal generating section, which generates a master period signal, and that operates based on the master period signal and (ii) a slave domain that includes a slave period signal generating section, which generates a slave period signal, and that operates based on the slave period signal. The master period signal generating section receives a control signal and resumes generation of the master period signal, which is being held, and the slave period signal generating section receives the control signal, initializes phase data of the slave period signal, and resumes generation of the slave period signal, which is being held.
摘要翻译：提供了一种测试被测设备的测试装置，包括：（i）主域，其包括主周期信号生成部分，其生成主周期信号，并且基于主周期信号进行操作;以及（ii）从机域，其包括从周期信号生成部分，其产生从周期信号，并且其基于从周期信号进行操作。主时段信号发生部分接收控制信号并恢复正在保持的主周期信号的产生，从周期信号产生部分接收控制信号，初始化从周期信号的相位数据，并恢复生成从时期信号，正在举行。

3. 发明申请

US20110199133A1 TEST APPARATUS AND TEST METHOD 失效
标题翻译：测试装置和测试方法
公开(公告)号：US20110199133A1
公开(公告)日：2011-08-18
申请号：US13024264
申请日：2011-02-09
申请人： Tatsuya YAMADA
发明人： Tatsuya YAMADA
IPC分类号： H03L7/00
CPC分类号： G01R31/31922
摘要： Provided is a test apparatus and a test method for substantially synchronizing phases of test signals for each of a plurality of clock domains. The test apparatus tests a device under test including a plurality of clock domains. The test apparatus comprises a period generator that generates a rate signal for determining a test period corresponding to an operation period of the device under test; a pattern generator that generates a test pattern; phase comparing sections that, for each clock domain, receive an operation clock signal of the clock domain acquired from a terminal of the device under test included in the clock domain, and detect a phase difference of the operation clock signal of the clock domain with respect to the rate signal; and a plurality of waveform shaping sections that are provided respectively to the clock domains, and that each shape a test signal based on the test pattern, according to the phase difference of the corresponding clock domain, to substantially synchronize the test signal with the operation clock signal of the corresponding clock domain.
摘要翻译：提供了一种用于基本上同步多个时钟域中的每一个的测试信号的相位的测试装置和测试方法。测试装置测试包括多个时钟域的被测器件。测试装置包括周期发生器，其产生用于确定对应于被测器件的操作周期的测试周期的速率信号; 生成测试图案的图案生成器; 相位比较部，对于每个时钟域，接收从被包括在时钟域中的被测器件的端子获取的时钟域的操作时钟信号，并且相对于时钟域的操作时钟信号的相位差相对于到速率信号; 以及多个波形整形部分，分别设置在时钟域上，并且根据相应的时钟域的相位差，基于测试图形来形成测试信号，以使测试信号与操作时钟基本上同步相应时钟域的信号。

4. 发明申请

US20130134429A1 THIN-FILM TRANSISTOR AND THIN-FILM TRANSISTOR MANUFACTURING METHOD 有权
标题翻译：薄膜晶体管和薄膜晶体管制造方法
公开(公告)号：US20130134429A1
公开(公告)日：2013-05-30
申请号：US13556542
申请日：2012-07-24
申请人： Tatsuya YAMADA
发明人： Tatsuya YAMADA
IPC分类号： H01L29/786 , H01L21/768
CPC分类号： H01L29/78678 , H01L23/53238 , H01L29/458 , H01L29/66765 , H01L29/7869 , H01L2924/0002 , H01L2924/00
摘要： A thin-film transistor according to the present disclosure includes: a substrate; a gate electrode above the substrate; a gate insulating layer on the gate electrode; a channel layer on the gate insulating layer which is located on the gate electrode; a source electrode above the channel layer; a drain electrode above the channel layer; and a barrier layer between the channel layer and the source electrode and between the channel layer and the drain electrode. Each of the source electrode and the drain electrode is made of a metal including copper, and the barrier layer contains nitrogen and molybdenum and has a density greater than 7.5 g/cm3 and less than 10.5 g/cm3.
摘要翻译：根据本公开的薄膜晶体管包括：衬底; 在基板上方的栅电极; 栅电极上的栅极绝缘层; 栅极绝缘层上的位于栅电极上的沟道层; 沟道层上方的源电极; 沟道层上方的漏电极; 以及沟道层和源电极之间以及沟道层和漏电极之间的阻挡层。源极电极和漏极电极由包含铜的金属制成，阻挡层含有氮和钼，密度大于7.5g / cm 3且小于10.5g / cm 3。

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