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1. 发明申请

US20220157951A1 HIGH VOLTAGE EDGE TERMINATION STRUCTURE FOR POWER SEMICONDCUTOR DEVICES AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20220157951A1
公开(公告)日：2022-05-19
申请号：US16950586
申请日：2020-11-17
申请人： Hamza YILMAZ , TAIWAN SEMICONDUCTOR CO., LTD.
发明人： Hamza YILMAZ , Aryadeep MRINAL
IPC分类号： H01L29/40 , H01L29/06 , H01L21/265
摘要： A high voltage edge termination structure for a power semiconductor device is provided. The high voltage edge termination structure comprises a semiconductor body of a first conductive type, a JTE region of a second conductive type, a heavily doped channel stop region of the first conductive type, and a plurality of field plates. The JTE region is formed in the semiconductor body, wherein the JTE region is adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed in the semiconductor body, wherein the heavily doped channel stop region is spaced apart from the JTE region. The plurality of field plates is formed on the JTE region.

2. 发明申请

US20220131000A1 SHIELDED GATE TRENCH MOSFET DEVICES 有权
公开(公告)号：US20220131000A1
公开(公告)日：2022-04-28
申请号：US17572645
申请日：2022-01-11
申请人： IPOWER SEMICONDUCTOR , Taiwan Semiconductor Co., Ltd.
发明人： HAMZA YILMAZ , JONG OH KIM
IPC分类号： H01L29/78 , H01L29/423 , H01L29/66
摘要： A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

3. 发明授权

US10034335B1 Switching mode constant current LED driver 有权
公开(公告)号：US10034335B1
公开(公告)日：2018-07-24
申请号：US15627239
申请日：2017-06-19
申请人： Taiwan Semiconductor Co., Ltd.
发明人： Wei-Chun Hsiao , Yueh-Hua Chiang
IPC分类号： H05B33/08
摘要： A switching mode constant current led driver including an energy transmission unit, an LED module, a power transistor, a resistor and a control unit, the control unit including a driving unit for generating a driving voltage signal, and a duty cycle determining unit for determining a duty cycle of the driving voltage signal, wherein, the duty cycle determining unit determines a charging time for a reference current to charge an external capacitor according to a present time length, and determines a discharging time for a discharging current to discharge the external capacitor according to an inductor discharging time, the discharging current being proportional to an average value of an inductor charging status signal, and a comparing voltage is thereby generated on the external capacitor; and compares the comparing voltage with a saw-tooth voltage to generate a next time length of the duty cycle.

4. 发明申请

US20180166423A1 COMMON-SOURCE PACKAGING STRUCTURE 审中-公开
公开(公告)号：US20180166423A1
公开(公告)日：2018-06-14
申请号：US15803248
申请日：2017-11-03
申请人： TAIWAN SEMICONDUCTOR CO., LTD.
发明人： Chien-Chung CHEN , Sen MAO , Hsin-Liang LIN
IPC分类号： H01L25/07 , H01L23/00 , H01L23/31
CPC分类号： H01L25/072 , H01L23/3121 , H01L24/06 , H01L24/40 , H01L24/48 , H01L2224/371 , H01L2224/40101 , H01L2224/40137 , H01L2224/40245 , H01L2224/48101 , H01L2224/48137 , H01L2924/00014 , H01L2924/13091 , H01L2224/84
摘要： A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.

5. 发明申请

US20180166422A1 COMMON-SOURCE PACKAGING STRUCTURE 审中-公开
公开(公告)号：US20180166422A1
公开(公告)日：2018-06-14
申请号：US15439268
申请日：2017-02-22
申请人： TAIWAN SEMICONDUCTOR CO., LTD.
发明人： Chien-Chung CHEN , Sen MAO , Hsin-Liang LIN
IPC分类号： H01L25/07 , H01L23/31 , H01L23/00
CPC分类号： H01L25/072 , H01L23/3121 , H01L24/06 , H01L24/40 , H01L24/48 , H01L2224/371 , H01L2224/40101 , H01L2224/40137 , H01L2224/40245 , H01L2224/48101 , H01L2224/48137 , H01L2924/00014 , H01L2924/13091 , H01L2224/84
摘要： A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.

6. 发明授权

US09997500B1 Common-source packaging structure 有权
公开(公告)号：US09997500B1
公开(公告)日：2018-06-12
申请号：US15439268
申请日：2017-02-22
申请人： TAIWAN SEMICONDUCTOR CO., LTD.
发明人： Chien-Chung Chen , Sen Mao , Hsin-Liang Lin
IPC分类号： H01L23/495 , H01L25/07 , H01L23/31 , H01L23/00
CPC分类号： H01L25/072 , H01L23/3121 , H01L24/06 , H01L24/40 , H01L24/48 , H01L2224/371 , H01L2224/40101 , H01L2224/40137 , H01L2224/40245 , H01L2224/48101 , H01L2224/48137 , H01L2924/00014 , H01L2924/13091 , H01L2224/84
摘要： A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.

7. 发明授权

US09905690B1 Field effect transistor having a multi-width electrode structure and method for manufacturing the same 有权
公开(公告)号：US09905690B1
公开(公告)日：2018-02-27
申请号：US15270498
申请日：2016-09-20
申请人： TAIWAN SEMICONDUCTOR CO., LTD.
发明人： Yi-Lung Tsai , Aryadeep Mrinal , Mohammad Amanullah , Po-Wen Yang , Shu-Siang Liang
IPC分类号： H01L29/40 , H01L21/306 , H01L21/311 , H01L21/285 , H01L29/49 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7831 , H01L21/28525 , H01L21/30604 , H01L21/31111 , H01L29/401 , H01L29/4236 , H01L29/42376 , H01L29/4916
摘要： A field effect transistor is manufactured by firstly forming an epitaxial layer on a substrate. Then, a trench having an oxide layer is formed on the epitaxial layer. The oxide layer has a first electrode portion having a first width and a first height and a second electrode portion having a second width and a second height. A gate oxide layer covering the oxide layer and the second electrode portion has a gate portion having a third width. The epitaxial layer has a body region and a source region, where these two regions are adjacent to the gate portion and covered by an interlayer dielectric. A source electrode covering the body region and the interlayer dielectric contacts the source region. The first height is no less than the second height, the first width is smaller than the second width, and the second width is smaller than the third width.

8. 发明授权

US09433045B2 Drive circuit with an external mode-adjusting pin 有权
标题翻译：带外部模式调节引脚的驱动电路
公开(公告)号：US09433045B2
公开(公告)日：2016-08-30
申请号：US14598453
申请日：2015-01-16
申请人： TAIWAN SEMICONDUCTOR CO., LTD.
发明人： Yueh-Hua Chiang
IPC分类号： H05B33/08 , H03K17/687
CPC分类号： H05B33/0815 , H03K17/687 , H05B33/0818 , H05B33/0845
摘要： A drive circuit with an external mode-adjusting pin includes an operational mode control circuit and a drive processing circuit. The operational mode control circuit further includes a current mirror circuit, a resistor, a capacitor and a comparator. The first comparator input port receives a reference voltage. The second comparator input port couples the second output port of the current mirror and the capacitor. The current mirror circuit bases on a resistor current to generate a charge current for charging the capacitor. As the charge voltage at the second comparator input port reaches a reference voltage, a trigger signal is outputted to the drive processing circuit for controlling the switches thereof. The external pin is defined to one end of the resistor or the capacitor for varying the resistance or the capacitance respectively to determine the operational mode for the driven circuit.
摘要翻译：具有外部模式调节引脚的驱动电路包括操作模式控制电路和驱动处理电路。操作模式控制电路还包括电流镜电路，电阻器，电容器和比较器。第一比较器输入端口接收参考电压。第二比较器输入端口连接电流镜的第二输出端口和电容器。电流镜电路基于电阻电流以产生用于对电容器充电的充电电流。当第二比较器输入端口的充电电压达到参考电压时，触发信号被输出到用于控制其开关的驱动处理电路。外部引脚被定义为电阻器或电容器的一端，用于分别改变电阻或电容，以确定驱动电路的工作模式。

9. 发明申请

US20160135259A1 DRIVE CIRCUIT WITH AN EXTERNAL MODE-ADJUSTING PIN 有权
标题翻译：具有外部模式调节PIN的驱动电路
公开(公告)号：US20160135259A1
公开(公告)日：2016-05-12
申请号：US14598453
申请日：2015-01-16
申请人： TAIWAN SEMICONDUCTOR CO., LTD.
发明人： YUEH-HUA CHIANG
IPC分类号： H05B33/08 , H03K17/687
CPC分类号： H05B33/0815 , H03K17/687 , H05B33/0818 , H05B33/0845
摘要： A drive circuit with an external mode-adjusting pin includes an operational mode control circuit and a drive processing circuit. The operational mode control circuit further includes a current mirror circuit, a resistor, a capacitor and a comparator. The first comparator input port receives a reference voltage. The second comparator input port couples the second output port of the current mirror and the capacitor. The current mirror circuit bases on a resistor current to generate a charge current for charging the capacitor. As the charge voltage at the second comparator input port reaches a reference voltage, a trigger signal is outputted to the drive processing circuit for controlling the switches thereof. The external pin is defined to one end of the resistor or the capacitor for varying the resistance or the capacitance respectively to determine the operational mode for the driven circuit.
摘要翻译：具有外部模式调节引脚的驱动电路包括操作模式控制电路和驱动处理电路。操作模式控制电路还包括电流镜电路，电阻器，电容器和比较器。第一比较器输入端口接收参考电压。第二比较器输入端口连接电流镜的第二输出端口和电容器。电流镜电路基于电阻电流以产生用于对电容器充电的充电电流。当第二比较器输入端口的充电电压达到参考电压时，触发信号被输出到用于控制其开关的驱动处理电路。外部引脚被定义为电阻器或电容器的一端，用于分别改变电阻或电容，以确定驱动电路的工作模式。

10. 发明授权

US08736012B2 Trenched semiconductor structure 有权
标题翻译：半导体结构薄
公开(公告)号：US08736012B2
公开(公告)日：2014-05-27
申请号：US13737252
申请日：2013-01-09
申请人： Taiwan Semiconductor Co., Ltd.
发明人： Chao-Hsin Huang , Chih-Chiang Chuang
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L21/26586 , H01L29/0661 , H01L29/407 , H01L29/47 , H01L29/8725
摘要： A trenched semiconductor structure comprises a semiconductor substrate, an epitaxial layer, an ion implantation layer, a termination region dielectric layer, an active region dielectric layer, and a first polysilicon layer. The epitaxial layer doped with impurities of a first conductive type is formed on the semiconductor substrate. A plurality of active region trenches and a termination region trench are formed in the epitaxial layer. The ion implantation layer is formed in the active region trenches by doping impurities of a second conductive type. The termination region dielectric layer covers the termination region trench. The active region dielectric layer covers the ion implantation region. The first polysilicon layer covers the active region dielectric layer and fills the active region trenches. The depth of the termination region trench is greater than that of the active region trenches and close to that of the depletion region under reverse breakdown.
摘要翻译：沟槽半导体结构包括半导体衬底，外延层，离子注入层，终端区介电层，有源区介电层和第一多晶硅层。掺杂有第一导电类型的杂质的外延层形成在半导体衬底上。在外延层中形成多个有源区沟槽和端接区沟槽。离子注入层通过掺杂第二导电类型的杂质形成在有源区沟槽中。端接区介电层覆盖端接区沟槽。有源区介电层覆盖离子注入区。第一多晶硅层覆盖有源区介电层并填充有源区沟槽。端接区沟槽的深度大于有源区沟槽的深度，并且靠近反向击穿时的耗尽区的深度。

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