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1. 发明申请

US20100160151A1 Method for manufacturing ammonia gas absorbent using Fe-zeolite 审中-公开
标题翻译：使用Fe-沸石制造氨气吸收剂的方法
公开(公告)号：US20100160151A1
公开(公告)日：2010-06-24
申请号：US12461034
申请日：2009-07-30
申请人： In Kook Bae , Young Nam Jang , Soo Chun Chae , Sung Ki Lee , Kyeoung Won Ryu
发明人： In Kook Bae , Young Nam Jang , Soo Chun Chae , Sung Ki Lee , Kyeoung Won Ryu
IPC分类号： B01J29/88
CPC分类号： B01D53/02 , B01D2253/108 , B01D2253/34 , B01D2257/406 , B01J20/183 , B01J20/186 , B01J20/3028 , B01J20/3042 , C01C1/12 , Y02P20/52
摘要： A method is developed for fabrication of an ammonia gas adsorbent using Fe-zeolite. This method uses Fe-zeolite obtained from municipal waste slag to prepare a gas adsorbent, thereby reusing molten slag as a specified waste so as to improve the value of the waste. To achieve the purpose, the method includes mixing Fe-zeolite powder with a forming adjuvant to prepare a mixture; adding a forming agent to the mixture to obtain a granular Fe-zeolite product; and drying and calcining the obtained granular Fe-zeolite product. Therefore, Fe-zeolite obtained from molten slag as a waste product can be reused as an ammonia gas adsorbent.
摘要翻译：开发了使用Fe-沸石制造氨气吸附剂的方法。该方法使用从城市废渣获得的Fe-沸石来制备气体吸附剂，从而将熔渣重新用作特定的废物，从而提高废物的价值。为了达到该目的，该方法包括将Fe-沸石粉末与成形助剂混合以制备混合物; 向混合物中加入成型剂以获得粒状Fe-沸石产物; 干燥并煅烧得到的粒状Fe-沸石产物。因此，作为废弃物从熔渣获得的Fe-沸石可以再利用为氨气吸附剂。

2. 发明申请

US20080073761A1 Semiconductor package and stacked semiconductor package 审中-公开
标题翻译：半导体封装和堆叠半导体封装
公开(公告)号：US20080073761A1
公开(公告)日：2008-03-27
申请号：US11589715
申请日：2006-10-31
申请人： Chan-min Han , Beung-seuck Song , Sung-ki Lee
发明人： Chan-min Han , Beung-seuck Song , Sung-ki Lee
IPC分类号： H01L23/495
CPC分类号： H01L23/49548 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L25/105 , H01L2224/32245 , H01L2224/45139 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2225/1029 , H01L2924/00014 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor package including at least one semiconductor chip and inner leads may be provided. The semiconductor package may include a semiconductor chip. A plurality of inner leads having upper surfaces and lower surfaces, may be electrically connected to the semiconductor chip, and may be spaced apart from the semiconductor chip. A molding resin may fix the semiconductor chip and the inner leads. The upper surfaces of the inner leads may be fixed to the molding resin, the lower surfaces of the inner leads may be exposed from the molding resin, and widths of the lower surfaces of the inner leads may be narrower than widths of the upper surfaces of the inner leads.
摘要翻译：可以提供包括至少一个半导体芯片和内部引线的半导体封装。半导体封装可以包括半导体芯片。具有上表面和下表面的多个内引线可以电连接到半导体芯片，并且可以与半导体芯片间隔开。模制树脂可以固定半导体芯片和内部引线。内引线的上表面可以固定到模制树脂上，内引线的下表面可以从模塑树脂露出，并且内引线的下表面的宽度可以比上表面的宽度窄内线。

3. 发明授权

US06011603A Double super twisted nematic liquid crystal display with improved pre-tilt angles 失效
标题翻译：具有改进的预倾角的双超扭曲向列型液晶显示器
公开(公告)号：US06011603A
公开(公告)日：2000-01-04
申请号：US971358
申请日：1997-11-17
申请人： Sung-ki Lee
发明人： Sung-ki Lee
IPC分类号： G02F1/133 , G02F1/1335 , G02F1/13363 , G02F1/1337 , G02F1/1347 , G02F1/139
CPC分类号： G02F1/133636 , G02F1/1337 , G02F1/133723 , G02F1/13471 , G02F1/1397
摘要： A double super twisted nematic (DSTN) liquid crystal display (LCD) is provided. The DSTN LCD includes: a liquid crystal display cell having first and second transparent substrates arranged parallel to each other, first and second orientation layers formed on opposing surfaces of the first and second transparent substrates, respectively, a liquid crystal sealed between the first and second transparent substrates, and indium tin oxide (ITO) electrodes formed on the opposing surfaces of the first and second transparent substrates while crossing each other; and a liquid crystal compensation cell having a third transparent substrate attached on the second transparent substrate, a fourth transparent substrate arranged in parallel to the third transparent substrate, third and fourth orientation layers formed on each opposing surface of the third and fourth orientation layers, and a liquid crystal sealed between the third and fourth orientation layers, wherein the pre-tilted angle of the liquid crystal sealed between the first and second orientation layers differs from the pre-tilted angle of the liquid crystal sealed between the third and fourth orientation layers such that the difference between changes in the refractive index anisotropies of the liquid crystals is compensated for.
摘要翻译：提供双超扭曲向列（DSTN）液晶显示器（LCD）。 DSTN LCD包括：具有彼此平行布置的第一和第二透明基板的液晶显示单元，分别形成在第一和第二透明基板的相对表面上的第一和第二取向层，密封在第一和第二透明基板之间的液晶透明基板和形成在第一和第二透明基板的相对表面上的铟锡氧化物（ITO）电极，同时彼此交叉; 以及具有安装在第二透明基板上的第三透明基板的液晶补偿单元，与第三透明基板平行布置的第四透明基板，形成在第三取向层和第四取向层的每个相对面上的第三取向层和第四取向层，密封在第三和第四取向层之间的液晶，其中密封在第一和第二取向层之间的液晶的预倾角与在第三和第四取向层之间密封的液晶的预倾斜角度不同，补偿液晶的折射率各向异性变化的差异。

4. 发明申请

US20090150698A1 HOST APPARATUS CONNECTED TO IMAGE FORMING APPARATUS AND POWER SAVE MODE CONTROL METHOD THEREOF 有权
标题翻译：连接到图像形成装置的主机装置和省电模式控制方法
公开(公告)号：US20090150698A1
公开(公告)日：2009-06-11
申请号：US12252622
申请日：2008-10-16
申请人： Sung-ki LEE
发明人： Sung-ki LEE
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , G06F1/3215 , G06F1/3284
摘要： A method of controlling a power save mode of an image forming apparatus connected to a host apparatus, the method includes: requesting information on a power mode of the image forming apparatus; transmitting the power mode information and information on an entering time for a power save mode of the image forming apparatus from the image forming apparatus; and displaying the entering time for the power save mode of the image forming apparatus on a basis of the entering time information.
摘要翻译：一种控制连接到主机装置的图像形成装置的节电模式的方法，所述方法包括：请求关于图像形成装置的功率模式的信息; 从图像形成装置发送关于图像形成装置的省电模式的输入时间的功率模式信息和信息; 并基于输入时间信息显示图像形成装置的省电模式的输入时间。

5. 发明申请

US20090026596A1 LEAD FRAME, SEMICONDUCTOR PACKAGE, AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME 审中-公开
标题翻译：引线框架，半导体封装和堆叠半导体封装
公开(公告)号：US20090026596A1
公开(公告)日：2009-01-29
申请号：US12178532
申请日：2008-07-23
申请人： Sang-Wook PARK , Jong-Gi LEE , Kun-Dae YEOM , Sung-Ki LEE , Ji-Seok HONG
发明人： Sang-Wook PARK , Jong-Gi LEE , Kun-Dae YEOM , Sung-Ki LEE , Ji-Seok HONG
IPC分类号： H01L23/495 , H05K7/18
CPC分类号： H01L23/49555 , H01L23/49548 , H01L24/48 , H01L25/105 , H01L2224/48091 , H01L2224/48247 , H01L2225/1029 , H01L2225/1064 , H01L2924/00014 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In certain embodiments, a lead frame includes a paddle, a plurality of inner leads, first outer leads, and a second outer lead. The plurality of inner leads can be arranged at a side face of the paddle. The first outer leads can extend from the inner leads along a first direction and can be arranged at a substantially central portion of the side face of the paddle. Furthermore, each of the first outer leads can have a first area. The second outer lead can be arranged at an edge portion of the side face of the paddle and can be supported by the paddle. The second outer lead can have a second area that is larger than the first area.
摘要翻译：在某些实施例中，引线框架包括桨，多个内引线，第一外引线和第二外导线。多个内引线可以布置在桨的侧面。第一外引线可以沿着第一方向从内引线延伸，并且可以布置在桨的侧面的大致中心部分。此外，每个第一外引线可以具有第一区域。第二外引线可以布置在桨的侧面的边缘部分处，并且可以由桨支撑。第二外部引线可以具有大于第一区域的第二区域。

6. 发明申请

US20080308913A1 STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：堆叠式半导体封装及其制造方法
公开(公告)号：US20080308913A1
公开(公告)日：2008-12-18
申请号：US12140190
申请日：2008-06-16
申请人： Sang-Wook PARK , Min-Young SON , Jong-Gi LEE , Kun-Dae YEOM , Sung-Ki LEE , Ji-Seok HONG
发明人： Sang-Wook PARK , Min-Young SON , Jong-Gi LEE , Kun-Dae YEOM , Sung-Ki LEE , Ji-Seok HONG
IPC分类号： H01L23/495
CPC分类号： H01L23/49555 , H01L24/48 , H01L25/105 , H01L2224/48247 , H01L2225/1029 , H01L2225/1064 , H01L2924/00014 , H01L2924/181 , H05K3/3426 , H05K2201/10515 , H05K2201/10689 , H05K2201/10757 , H05K2201/10969 , H05K2201/2036 , Y02P70/613 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked semiconductor package includes a first semiconductor package, a second semiconductor package and a conductive connection member. The first semiconductor package includes a first semiconductor chip, a first lead frame having first outer leads that are electrically connected to the first semiconductor chip, and a first molding member formed on the first semiconductor chip and the first lead frame to expose the first outer leads. The second semiconductor package includes a second semiconductor chip, a second lead frame formed on the first molding member and having second outer leads that may be electrically connected to the second semiconductor chip, and a second molding member formed on the second semiconductor chip and the second lead frame to expose the second outer leads. The conductive connection member may electrically connect the first outer leads and the second outer leads to each other. Further, the conductive connection member may have a crack-blocking groove.
摘要翻译：叠层半导体封装包括第一半导体封装，第二半导体封装和导电连接构件。第一半导体封装包括第一半导体芯片，具有与第一半导体芯片电连接的第一外部引线的第一引线框架和形成在第一半导体芯片和第一引线框架上以暴露第一外部引线的第一模制构件。第二半导体封装包括第二半导体芯片，形成在第一模制构件上的第二引线框架，并且具有可与第二半导体芯片电连接的第二外部引线，以及形成在第二半导体芯片上的第二模制构件和第二半导体芯片引线框架露出第二个外引线。导电连接构件可以将第一外引线和第二外引线彼此电连接。此外，导电连接构件可以具有防裂槽。

7. 发明授权

US08516286B2 Host apparatus connected to image forming apparatus and power save mode control method thereof 有权
公开(公告)号：US08516286B2
公开(公告)日：2013-08-20
申请号：US12252622
申请日：2008-10-16
申请人： Sung-ki Lee
发明人： Sung-ki Lee
IPC分类号： G06F1/00 , G03G15/00
CPC分类号： G06F1/26 , G06F1/3215 , G06F1/3284
摘要： A method of controlling a power save mode of an image forming apparatus connected to a host apparatus, the method includes: requesting information on a power mode of the image forming apparatus; transmitting the power mode information and information on an entering time for a power save mode of the image forming apparatus from the image forming apparatus; and displaying the entering time for the power save mode of the image forming apparatus on a basis of the entering time information.

8. 发明申请

US20140063607A1 PRINTED MATERIAL AND PHOTOGRAPHIC MATERIAL 有权
标题翻译：印刷材料和摄影材料
公开(公告)号：US20140063607A1
公开(公告)日：2014-03-06
申请号：US14006802
申请日：2012-03-30
申请人： Tomoo Fukuda , Mitsuo Arima , Sung-Ki Lee , Yu Nomura , Hiroyuki Kiso , Fumihiko Iida
发明人： Tomoo Fukuda , Mitsuo Arima , Sung-Ki Lee , Yu Nomura , Hiroyuki Kiso , Fumihiko Iida
IPC分类号： G02B1/11
CPC分类号： G02B1/118 , G02B27/42
摘要： A printed material includes a printed material body with a surface, and an optical element disposed on the surface of the printed material body. The optical element includes multiple structures formed at a pitch not longer than the wavelength of visible light. The structures have an aspect ratio of 0.6 or more and 5.0 or less.
摘要翻译：印刷材料包括具有表面的印刷材料体和设置在印刷材料体的表面上的光学元件。光学元件包括以不超过可见光波长的间距形成的多个结构。该结构的纵横比为0.6以上且5.0以下。

9. 发明申请

US20090057916A1 SEMICONDUCTOR PACKAGE AND APPARATUS USING THE SAME 审中-公开
标题翻译：半导体封装和使用它的设备
公开(公告)号：US20090057916A1
公开(公告)日：2009-03-05
申请号：US12198731
申请日：2008-08-26
申请人： Kun-Dae YEOM , Sang-Wook PARK , Sung-Ki LEE
发明人： Kun-Dae YEOM , Sang-Wook PARK , Sung-Ki LEE
IPC分类号： H01L23/49
CPC分类号： H01L25/0657 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4912 , H01L2224/49175 , H01L2224/73265 , H01L2224/83 , H01L2224/92247 , H01L2225/0651 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01083 , H01L2924/014 , H01L2924/07802 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor package is provided. The semiconductor package comprises a substrate having a top surface and a bottom surface, a first semiconductor chip having a plurality of bonding pad regions electrically connected to the substrate by a plurality of first bonding wires, a spacer tape covering the active surface of the first semiconductor chip excluding the plurality of bonding pad regions, and a second semiconductor chip mounted on the active surface of the first semiconductor chip with the spacer interposed.
摘要翻译：提供半导体封装。半导体封装包括具有顶表面和底表面的衬底，第一半导体芯片，具有通过多个第一接合线电连接到衬底的多个接合焊盘区域;覆盖第一半导体的有源表面的隔离带芯片，不包括多个接合焊盘区域，以及安装在第一半导体芯片的有源表面上的第二半导体芯片，其间隔开。

10. 发明申请

US20060151878A1 Semiconductor chip packaging apparatus and method of manufacturing semiconductor chip package 审中-公开
标题翻译：半导体芯片封装装置及半导体芯片封装的制造方法
公开(公告)号：US20060151878A1
公开(公告)日：2006-07-13
申请号：US11326192
申请日：2006-01-06
申请人： Se-Young Jeong , Nam-Seog Kim , Sung-Ki Lee , Hee-Kook Choi , Ki-Kwon Jeong , Tae-Sung Park , Yoshikuni Nakadaira , Sang-Hyeop Lee , Sung-Hwan Kim
发明人： Se-Young Jeong , Nam-Seog Kim , Sung-Ki Lee , Hee-Kook Choi , Ki-Kwon Jeong , Tae-Sung Park , Yoshikuni Nakadaira , Sang-Hyeop Lee , Sung-Hwan Kim
IPC分类号： H01L23/48
CPC分类号： H01L23/49582 , H01L21/4835 , H01L2924/00014 , H01L2924/0002 , H01L2224/45099 , H01L2924/00
摘要： Example embodiments of a semiconductor chip packaging apparatus and method thereof are disclosed. The packaging apparatus may include a plating unit to perform a conductive plating process to form a conductive plating layer on external terminals of a semiconductor chip package, and a reflow unit adapted to melt the conductive plating layer. The plating unit and reflow unit may be disposed in a single line with the plating module. Thus, it is possible to effectively suppress the growth of whiskers on the plating layer of the external terminals, and to secure economical efficiency, reducing costs, and allowing mass production.
摘要翻译：公开了半导体芯片封装装置及其方法的示例性实施例。包装装置可以包括电镀单元，用于执行导电电镀工艺以在半导体芯片封装的外部端子上形成导电镀层，以及适于熔化导电镀层的回流单元。电镀单元和回流单元可以与电镀模块一起设置。因此，可以有效地抑制外部端子的镀层上的晶须的生长，并且能够确保经济效益，降低成本，并且能够批量生产。

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