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1. 发明申请

US20130097613A1 APPARTUS AND METHOD FOR THREAD PROGRESS TRACKING 有权
标题翻译：用于进行进度跟踪的方法和方法
公开(公告)号：US20130097613A1
公开(公告)日：2013-04-18
申请号：US13588228
申请日：2012-08-17
申请人： Young Sam Shin , Seung Won Lee , Min Young Son , Shi Hwa Lee
发明人： Young Sam Shin , Seung Won Lee , Min Young Son , Shi Hwa Lee
IPC分类号： G06F9/46
CPC分类号： G06F9/485 , G06F9/30123 , G06F11/3409 , G06F11/3466 , G06F11/3636 , G06F2209/508
摘要： Provided is a method and apparatus for measuring a progress or a performance of an application program in a computing environment using a micro-architecture. An apparatus for thread progress tracking may select a thread included in an application program, may determine, based on a predetermined criterion, whether an execution scheme for at least one instruction included in the thread corresponds to an effective execution scheme in which an execution time is uniform or a non-effective execution scheme in which a delayed cycle is included and the execution time is non-uniform, and may generate an effective progress index (EPI) by accumulating an execution time of an instruction executed by the effective execution scheme other than an instruction executed by the non-effective execution scheme.
摘要翻译：提供了一种用于在使用微架构的计算环境中测量应用程序的进度或性能的方法和装置。用于线程进度跟踪的装置可以选择包括在应用程序中的线程，可以基于预定标准来确定包括在线程中的至少一条指令的执行方案是否对应于执行时间为统一或非有效的执行方案，其中包括延迟循环并且执行时间不均匀，并且可以通过累积由除了有效执行方案之外的有效执行方案执行的指令的执行时间来生成有效进度索引（EPI）由非有效执行方案执行的指令。

2. 发明授权

US08116088B2 Semiconductor package and method of forming the same, and printed circuit board 有权
标题翻译：半导体封装及其形成方法，以及印刷电路板
公开(公告)号：US08116088B2
公开(公告)日：2012-02-14
申请号：US12116123
申请日：2008-05-06
申请人： Mu-Seob Shin , Min-Young Son , Tae-Sung Yoon , Young-Hee Song , Byung-Seo Kim
发明人： Mu-Seob Shin , Min-Young Son , Tae-Sung Yoon , Young-Hee Song , Byung-Seo Kim
IPC分类号： H05K1/11 , H05K3/34 , H01L23/02 , H01L23/48
CPC分类号： H01L23/13 , H01L23/3128 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L24/97 , H01L25/105 , H01L2224/05553 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/484 , H01L2224/49171 , H01L2224/73215 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Provided are a semiconductor package, a method of forming the semiconductor package, and a printed circuit board (PCB). The semiconductor package includes: a PCB including at least two parts divided by an isolation region; a semiconductor chip mounted on the PCB; and a molding layer disposed in the isolation region. The method includes: preparing a PCB, the PCB including a plurality of chip regions and a scribe region; forming isolation regions dividing each of the chip regions into two parts, the isolation regions including inner isolation regions and outer isolation regions, the inner isolation regions being provided in the chip regions, the outer isolation regions being provided at both ends of the inner isolation regions so as to extend toward the scribe region; mounting semiconductor chips on the chip regions; and cutting the PCB along the scribe region to divide the chip regions into at least two parts.
摘要翻译：提供半导体封装，形成半导体封装的方法和印刷电路板（PCB）。半导体封装包括：PCB，其包括由隔离区域划分的至少两个部分; 安装在PCB上的半导体芯片; 以及设置在隔离区域中的成型层。该方法包括：准备PCB，PCB包括多个芯片区域和划线区域; 形成将每个芯片区域分成两部分的隔离区域，隔离区域包括内部隔离区域和外部隔离区域，内部隔离区域设置在芯片区域中，外部隔离区域设置在内部隔离区域的两端以扩展到划刻区域; 将半导体芯片安装在芯片区域上; 以及沿着划线区域切割PCB以将芯片区域分成至少两个部分。

3. 发明申请

US20120023505A1 APPARATUS AND METHOD FOR THREAD SCHEDULING AND LOCK ACQUISITION ORDER CONTROL BASED ON DETERMINISTIC PROGRESS INDEX 有权
标题翻译：基于确定性进度指标的螺纹调度和锁定采集订单控制的装置和方法
公开(公告)号：US20120023505A1
公开(公告)日：2012-01-26
申请号：US13099453
申请日：2011-05-03
申请人： Young Sam SHIN , Seung Won LEE , Min Young SON , Shi Hwa LEE
发明人： Young Sam SHIN , Seung Won LEE , Min Young SON , Shi Hwa LEE
IPC分类号： G06F9/46
CPC分类号： G06F9/526 , G06F9/4881
摘要： Provided is a method and apparatus for ensuring a deterministic execution characteristic of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A lock controlling apparatus based on a deterministic progress index (DPI) may include a loading unit to load a DPI of a first core and a DPI of a second core among DPIs of a plurality of cores at a lock acquisition point in time of each thread, a comparison unit to compare the DPI of the first core and the DPI of the second core, and a controller to assign a lock to a thread of the first core when the DPI of the first core is less than the DPI of the second core and when the second core corresponds to a last core to be compared among the plurality of cores.
摘要翻译：提供了一种用于确保应用程序的确定性执行特性以执行数据处理并且在使用微架构的计算环境中执行特定功能的方法和装置。基于确定性进度指标（DPI）的锁定控制装置可以包括加载单元，用于在每个线程的锁定获取点处在多个核心的DPI中加载第一核心的DPI和第二核心的DPI 比较单元，用于比较第一核心的DPI和第二核心的DPI;以及控制器，当第一核心的DPI小于第二核心的DPI时，分配锁定到第一核心的线程并且当第二核心对应于在多个核心之间要比较的最后一个核心时。

4. 发明授权

US08004091B2 Semiconductor package, method of fabricating the same, and semiconductor package mold 有权
标题翻译：半导体封装，其制造方法以及半导体封装模具
公开(公告)号：US08004091B2
公开(公告)日：2011-08-23
申请号：US12078598
申请日：2008-04-02
申请人： Seung-yeol Yang , Sang-wook Park , Seung-jae Lee , Min-young Son
发明人： Seung-yeol Yang , Sang-wook Park , Seung-jae Lee , Min-young Son
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L23/49838 , H01L21/565 , H01L23/3128 , H01L23/49833 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/49174 , H01L2224/73265 , H01L2225/0651 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes one or more semiconductor chips to form a semiconductor package. The semiconductor package may include a first semiconductor chip package having a first substrate including a first surface having a center portion on which a first semiconductor chip is mounted, at least one first boundary portion on which a plurality of conductive connection pad groups are formed, and/or a molding member including a body that covers the first semiconductor chip and at least one extension that extends from the body. The extension extends while avoiding the conductive connection pad group. The semiconductor package may further include a second semiconductor chip package stacked on the first semiconductor chip package and including a second substrate on which at least one second semiconductor chip that is electrically connected to the conductive connection pad group may be mounted.
摘要翻译：半导体封装包括一个或多个半导体芯片以形成半导体封装。半导体封装可以包括具有第一衬底的第一半导体芯片封装，第一衬底包括具有安装有第一半导体芯片的中心部分的第一表面，形成有多个导电连接焊盘组的至少一个第一边界部分，以及 /或包括覆盖第一半导体芯片的主体和从主体延伸的至少一个延伸部的模制构件。延长延伸，同时避免导电连接焊盘组。半导体封装还可以包括堆叠在第一半导体芯片封装上并包括第二衬底的第二半导体芯片封装，其上可以安装电连接到导电连接焊盘组的至少一个第二半导体芯片。

5. 发明申请

US20100146163A1 MEMORY DEVICE AND MANAGEMENT METHOD OF MEMORY DEVICE 有权
标题翻译：存储器件的存储器件和管理方法
公开(公告)号：US20100146163A1
公开(公告)日：2010-06-10
申请号：US12470574
申请日：2009-05-22
申请人： Min Young Son , Gyu Sang Choi , Jae Don Lee , Choong Hun Lee
发明人： Min Young Son , Gyu Sang Choi , Jae Don Lee , Choong Hun Lee
IPC分类号： G06F12/02 , G06F3/00 , G06F12/00
CPC分类号： G06F12/0246 , G06F12/123 , G06F2212/7203
摘要： A memory device and a method of managing a memory are provided. The memory device includes a command queue configured to receive a first command from a host to store the first command, and to read and transmit the first command, a controller configured to read, from a storage device, data corresponding to the first command transmitted from the command queue, and to store the data in a buffer memory, and a first memory configured to store a data list of data stored in the buffer memory, wherein, in response to the command queue receiving the first command from the host, the controller updates the data list of data stored in the first memory.
摘要翻译：提供了存储器件和管理存储器的方法。所述存储装置包括：命令队列，被配置为从主机接收第一命令以存储所述第一命令，并且读取和发送所述第一命令;控制器，被配置为从存储设备读取与从所述第一命令发送的第一命令相对应的数据; 命令队列，并将数据存储在缓冲存储器中，以及第一存储器，被配置为存储存储在缓冲存储器中的数据的数据列表，其中响应于命令队列从主机接收到第一命令，控制器更新存储在第一存储器中的数据的数据列表。

6. 发明授权

US07589405B2 Memory cards and method of fabricating the memory cards 失效
标题翻译：存储卡和制造存储卡的方法
公开(公告)号：US07589405B2
公开(公告)日：2009-09-15
申请号：US11286058
申请日：2005-11-23
申请人： Min-Young Son , Woo-Dong Lee
发明人： Min-Young Son , Woo-Dong Lee
IPC分类号： H01L23/02
CPC分类号： H01L23/5388 , H01L23/3121 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0655 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/181 , H01L2924/1815 , H01L2924/19105 , H05K3/284 , H05K3/3452 , H05K2201/0919 , H05K2201/0989 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided are a memory card and a method of fabricating the memory card. The memory card includes: a printed circuit board including conductive wires exposed to at least a portion of an outer wall of the printed circuit board; at least one electronic device mounted on the printed circuit board; and a molding part sealing the at least one electronic device on the printed circuit board and the conductive wires exposed to the outer wall of the printed circuit board, and simultaneously exposing at least a portion of the outer wall of the printed circuit board.
摘要翻译：提供了存储卡和制造存储卡的方法。存储卡包括：印刷电路板，包括暴露于印刷电路板的外壁的至少一部分的导线; 安装在印刷电路板上的至少一个电子装置; 以及密封印刷电路板上的至少一个电子器件和暴露于印刷电路板的外壁的导电线的成型部件，并且同时暴露印刷电路板的外壁的至少一部分。

7. 发明授权

US08943503B2 Apparatus and method for thread progress tracking using deterministic progress index 有权
标题翻译：使用确定性进度指标进行线程进度跟踪的装置和方法
公开(公告)号：US08943503B2
公开(公告)日：2015-01-27
申请号：US13156492
申请日：2011-06-09
申请人： Young Sam Shin , Seung Won Lee , Shi Hwa Lee , Suk Jin Kim , Min Young Son
发明人： Young Sam Shin , Seung Won Lee , Shi Hwa Lee , Suk Jin Kim , Min Young Son
IPC分类号： G06F9/46 , G06F11/34
CPC分类号： G06F11/3466 , G06F11/3423 , G06F2201/88
摘要： Provided is a method and apparatus for measuring a performance or a progress state of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A thread progress tracking apparatus may include a selector to select at least one thread constituting an application program; a determination unit to determine, based on a predetermined criterion, whether an instruction execution scheme corresponds to a deterministic execution scheme having a regular cycle or a nondeterministic execution scheme having an irregular delay cycle with respect to each of at least one instruction constituting a corresponding thread; and a deterministic progress counter to generate a deterministic progress index with respect to an instruction that is executed by the deterministic execution scheme, excluding an instruction that is executed by the nondeterministic execution scheme.
摘要翻译：提供了一种用于测量应用程序的性能或进展状态以便在使用微架构的计算环境中执行数据处理并执行特定功能的方法和装置。线程进度跟踪装置可以包括：选择器，用于选择构成应用程序的至少一个线程; 确定单元，基于预定标准，确定指令执行方案是否对应于具有规则周期的确定性执行方案或具有相对于构成对应线程的至少一个指令中的每一个指令具有不规则延迟周期的非确定性执行方案 ; 以及确定性进度计数器，用于生成关于由确定性执行方案执行的指令的确定性进度索引，不包括由非确定性执行方案执行的指令。

8. 发明授权

US08745339B2 Multi-core system and method for processing data in parallel in multi-core system 有权
标题翻译：多核系统并行处理数据的多核系统及方法
公开(公告)号：US08745339B2
公开(公告)日：2014-06-03
申请号：US13305163
申请日：2011-11-28
申请人： Min Young Son , Shi Hwa Lee , Seung Woo Lee , Young Sam Shin
发明人： Min Young Son , Shi Hwa Lee , Seung Woo Lee , Young Sam Shin
IPC分类号： G06F12/00
CPC分类号： G06F9/5027 , G06F2212/251
摘要： A multi-core system and a method for processing data in parallel in the multi-core system are provided. In the multi-core system, partitioning and allocating of data may be dynamically controlled based on local memory information. Thus, it is possible to increase an availability of a Central Processing Unit (CPU) and a local memory, and is possible to improve a performance of data parallel processing.
摘要翻译：提供了一种多核系统和一种在多核系统中并行处理数据的方法。在多核系统中，可以基于本地存储器信息来动态地控制数据的分配和分配。因此，可以增加中央处理单元（CPU）和本地存储器的可用性，并且可以提高数据并行处理的性能。

9. 发明授权

US08555289B2 System and method for dynamically managing tasks for data parallel processing on multi-core system 有权
标题翻译：用于动态管理多核系统数据并行处理任务的系统和方法
公开(公告)号：US08555289B2
公开(公告)日：2013-10-08
申请号：US12923793
申请日：2010-10-07
申请人： Min Young Son , Shi Hwa Lee , Seung Won Lee , Jeong Joon Yoo , Jae Don Lee , Young Sam Shin
发明人： Min Young Son , Shi Hwa Lee , Seung Won Lee , Jeong Joon Yoo , Jae Don Lee , Young Sam Shin
IPC分类号： G06F9/46
CPC分类号： G06F9/5088
摘要： A dynamic task management system and method for data parallel processing on a multi-core system are provided. The dynamic task management system may generate a registration signal for a task to be parallel processed, may generate a dynamic management signal used to dynamically manage at least one task, in response to the generated registration signal, and may control the at least one task to be created or cancelled in at least one core in response to the generated dynamic management signal.
摘要翻译：提供了一种用于多核系统上数据并行处理的动态任务管理系统和方法。动态任务管理系统可以生成用于待并行处理的任务的注册信号，可以响应于所生成的注册信号而生成用于动态管理至少一个任务的动态管理信号，并且可以将至少一个任务控制为响应于所生成的动态管理信号在至少一个核心中创建或取消。

10. 发明授权

US08356135B2 Memory device and control method 有权
标题翻译：存储器和控制方法
公开(公告)号：US08356135B2
公开(公告)日：2013-01-15
申请号：US12470552
申请日：2009-05-22
申请人： Min Young Son , Gyu Sang Choi , Jae Don Lee , Choong Hun Lee
发明人： Min Young Son , Gyu Sang Choi , Jae Don Lee , Choong Hun Lee
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： A memory device includes a first controller and a second controller. The first controller receives a first command from a host and stores the first command in a first command queue, and transmits the first command to the second controller relating to the first command stored in the first command queue. The second controller transmits the first command stored in the second command queue to a flash memory.
摘要翻译：存储装置包括第一控制器和第二控制器。第一控制器从主机接收第一命令并将第一命令存储在第一命令队列中，并且将第一命令发送到与存储在第一命令队列中的第一命令相关的第二控制器。第二控制器将存储在第二命令队列中的第一命令发送到闪速存储器。

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