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1. 发明授权

US07864613B2 Thermal code transmission circuit and semiconductor memory device using the same 有权
标题翻译：热代码传输电路和半导体存储器件使用相同
公开(公告)号：US07864613B2
公开(公告)日：2011-01-04
申请号：US12156836
申请日：2008-06-05
申请人： Sun Mo An , Youk Hee Kim
发明人： Sun Mo An , Youk Hee Kim
IPC分类号： G11C13/00 , G11C1/12
CPC分类号： G11C7/04 , G11C7/1051 , G11C7/1063 , G11C11/406 , G11C11/40626 , G11C11/4093 , G11C2211/4061
摘要： Disclosed are a thermal code transmission circuit and a semiconductor memory device using the same. The thermal code transmission circuit includes a select signal generator which generates a select signal in response to a first enable signal, a level signal generator which receives the first enable signal to generate a level signal, an update signal generator which receives the level signal and a first update signal to generate a second update signal, a latch unit which receives a thermal code in response to the second update signal and outputs the thermal code as an output thermal code, and a thermal code output unit which selectively outputs the output thermal code in response to the select signal.
摘要翻译：公开了热代码传输电路和使用其的半导体存储器件。热代码传输电路包括响应于第一使能信号产生选择信号的选择信号发生器，接收第一使能信号以产生电平信号的电平信号发生器，接收电平信号的更新信号发生器和第一更新信号以产生第二更新信号;锁存单元，其响应于所述第二更新信号接收热代码并输出所述热代码作为输出热代码;以及热代码输出单元，其选择性地输出所述输出热代码响应选择信号。

2. 发明申请

US20090168589A1 Thermal code transmission circuit and semiconductor memory device using the same 有权
标题翻译：热代码传输电路和半导体存储器件使用相同
公开(公告)号：US20090168589A1
公开(公告)日：2009-07-02
申请号：US12156836
申请日：2008-06-05
申请人： Sun Mo An , Youk Hee Kim
发明人： Sun Mo An , Youk Hee Kim
IPC分类号： G11C13/00 , H03M1/12
CPC分类号： G11C7/04 , G11C7/1051 , G11C7/1063 , G11C11/406 , G11C11/40626 , G11C11/4093 , G11C2211/4061
摘要： Disclosed are a thermal code transmission circuit and a semiconductor memory device using the same. The thermal code transmission circuit includes a select signal generator which generates a select signal in response to a first enable signal, a level signal generator which receives the first enable signal to generate a level signal, an update signal generator which receives the level signal and a first update signal to generate a second update signal, a latch unit which receives a thermal code in response to the second update signal and outputs the thermal code as an output thermal code, and a thermal code output unit which selectively outputs the output thermal code in response to the select signal.
摘要翻译：公开了热代码传输电路和使用其的半导体存储器件。热代码传输电路包括响应于第一使能信号产生选择信号的选择信号发生器，接收第一使能信号以产生电平信号的电平信号发生器，接收电平信号的更新信号发生器和第一更新信号以产生第二更新信号;锁存单元，其响应于所述第二更新信号接收热代码并输出所述热代码作为输出热代码;以及热代码输出单元，其选择性地输出所述输出热代码响应选择信号。

3. 发明申请

US20090046525A1 WAFER BURN-IN TEST CIRCUIT 失效
标题翻译： WAFER BURN测试电路
公开(公告)号：US20090046525A1
公开(公告)日：2009-02-19
申请号：US12179491
申请日：2008-07-24
申请人： Youk Hee Kim , Sun Mo An
发明人： Youk Hee Kim , Sun Mo An
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/06 , G11C29/006
摘要： A wafer burn-in test circuit includes an address toggle signal generating unit for generating an address toggle signal in response to address signals having a constant time period, a reset signal generating unit for receiving a wafer burn-in mode activation signal, the address signals, and a reset determination signal among the address signals and then generating a reset signal, a refresh test mode signal generating unit for receiving the address toggle signal and the reset signal and then generating a refresh test mode signal, and a refresh period signal generating unit for receiving the address toggle signal and the refresh test mode signal and then generating a refresh period signal.
摘要翻译：晶片老化测试电路包括：地址触发信号产生单元，用于响应于具有恒定时间段的地址信号产生地址触发信号;复位信号产生单元，用于接收晶片老化模式激活信号;地址信号，以及地址信号中的复位确定信号，然后产生复位信号;刷新测试模式信号产生单元，用于接收地址触发信号和复位信号，然后产生刷新测试模式信号;以及刷新周期信号产生单元用于接收地址切换信号和刷新测试模式信号，然后产生刷新周期信号。

4. 发明授权

US07779317B2 Test control circuit and reference voltage generating circuit having the same 有权
标题翻译：测试控制电路和参考电压发生电路具有相同的功能
公开(公告)号：US07779317B2
公开(公告)日：2010-08-17
申请号：US11963463
申请日：2007-12-21
申请人： Youk Hee Kim
发明人： Youk Hee Kim
IPC分类号： G01R31/28 , G01V3/00
CPC分类号： G01R31/31724 , G01R31/3004
摘要： A test control circuit according to an embodiment of the invention includes a test mode control unit that outputs a control signal according to a voltage trimming test signal, a decoding portion that receives the control signal and outputs a decoding signal, and a trimming signal adjusting portion that receives the decoding signal and outputs a trimming signal adjusted by a low level test signal.
摘要翻译：根据本发明的实施例的测试控制电路包括测试模式控制单元，其根据电压调整测试信号输出控制信号，接收控制信号并输出解码信号的解码部分和修整信号调整部分其接收解码信号并输出由低电平测试信号调整的微调信号。

5. 发明授权

US08023339B2 Pipe latch circuit and semiconductor memory device using the same 有权
标题翻译：管路锁存电路和使用其的半导体存储器件
公开(公告)号：US08023339B2
公开(公告)日：2011-09-20
申请号：US12459106
申请日：2009-06-26
申请人： Youk Hee Kim , Bok Rim Ko , Young Joo Kim
发明人： Youk Hee Kim , Bok Rim Ko , Young Joo Kim
IPC分类号： G11C11/00
CPC分类号： G11C7/1051 , G11C7/1039 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222
摘要： A pipe latch circuit comprises a reset signal generating unit which receives a read-write flag signal and a read period signal and generates a reset signal, wherein the reset signal is enabled upon entry into a write operation or after all data are outputted to an outside upon read operation, an input/output control signal generating unit which generates a plurality of input control signals and output control signals in response to a read strobe signal and a clock signal, and is reset in response to the reset signal, and a pipe latch unit which latches inputted data in response to the input control signals and outputs the latched data in response to the output control signals.
摘要翻译：管锁存电路包括复位信号产生单元，其接收读写标志信号和读周期信号并产生复位信号，其中复位信号在进入写操作或所有数据输出到外部之后被使能在读取操作时，输入/输出控制信号产生单元，其响应于读取选通信号和时钟信号产生多个输入控制信号并输出控制信号，并且响应于复位信号被复位，并且管闩锁单元，其响应于输入控制信号锁存输入数据，并响应于输出控制信号输出锁存数据。

6. 发明授权

US08331179B2 Precharge signal generator and semiconductor memory device 有权
标题翻译：预充电信号发生器和半导体存储器件
公开(公告)号：US08331179B2
公开(公告)日：2012-12-11
申请号：US12647786
申请日：2009-12-28
申请人： Youk Hee Kim
发明人： Youk Hee Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/20 , G11C7/22
摘要： A precharge signal generator having a latch signal generator, an internal signal generator, and a pulse generator is presented. The latch signal generator is configured to generate a latch signal that is activated in response to an auto-precharge command and inactivated in response to an active pulse. The internal signal generator is configured to generate an internal signal activated when a delayed active signal and the latch signal are all activated. The pulse generator is configured to generate a precharge signal including a pulse that is activated in a period for which the internal signal is being active.
摘要翻译：提出了具有锁存信号发生器，内部信号发生器和脉冲发生器的预充电信号发生器。锁存信号发生器被配置为产生响应于自动预充电命令被激活并且响应于有效脉冲而失活的锁存信号。内部信号发生器被配置为当延迟的有效信号和锁存信号全部被激活时，产生激活的内部信号。脉冲发生器被配置为产生包括在内部信号有效的时段中被激活的脉冲的预充电信号。

7. 发明授权

US07863947B2 Driving strength control circuit and data output circuit in semiconductor device 有权
标题翻译：半导体器件中的驱动强度控制电路和数据输出电路
公开(公告)号：US07863947B2
公开(公告)日：2011-01-04
申请号：US12215722
申请日：2008-06-30
申请人： Bok Rim Ko , Youk Hee Kim
发明人： Bok Rim Ko , Youk Hee Kim
IPC分类号： H03K19/003 , H03K19/08 , G11C11/4096
CPC分类号： H03K19/018585
摘要： A driving strength control circuit and a data output circuit for controlling driving strength of a data driver based on a user's demand are provided to make it possible to control the driving strength through a fuse cutting. The driving strength control circuit includes a fuse signal generating unit for generating a fuse signal based on a fuse cutting, a select signal generating unit for generating select signals in response to the fuse signal, a driving control signal generating unit for receiving set-up signals and generate driving control signals in response to the select signals, and a driving signal generating unit for driving signals by decoding the driving control signals.
摘要翻译：提供了驱动强度控制电路和数据输出电路，用于根据用户的要求来控制数据驱动器的驱动强度，以便通过熔丝切割来控制驱动强度。驱动强度控制电路包括用于根据熔丝切断产生熔丝信号的熔丝信号产生单元，用于响应于熔丝信号产生选择信号的选择信号产生单元，用于接收建立信号的驱动控制信号产生单元并且响应于选择信号产生驱动控制信号;以及驱动信号产生单元，用于通过解码驱动控制信号来驱动信号。

8. 发明申请

US20100246279A1 Pipe latch circuit and semiconductor memory device using the same 有权
标题翻译：管路锁存电路和使用其的半导体存储器件
公开(公告)号：US20100246279A1
公开(公告)日：2010-09-30
申请号：US12459106
申请日：2009-06-26
申请人： Youk Hee Kim , Bok Rim Ko , Young Joo Kim
发明人： Youk Hee Kim , Bok Rim Ko , Young Joo Kim
IPC分类号： G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1051 , G11C7/1039 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222
摘要： A pipe latch circuit comprises a reset signal generating unit which receives a read-write flag signal and a read period signal and generates a reset signal, wherein the reset signal is enabled upon entry into a write operation or after all data are outputted to an outside upon read operation, an input/output control signal generating unit which generates a plurality of input control signals and output control signals in response to a read strobe signal and a clock signal, and is reset in response to the reset signal, and a pipe latch unit which latches inputted data in response to the input control signals and outputs the latched data in response to the output control signals.
摘要翻译：管锁存电路包括复位信号发生单元，其接收读写标志信号和读周期信号并产生复位信号，其中复位信号在进入写操作时或在所有数据输出到外部之后被使能在读取操作时，输入/输出控制信号产生单元，其响应于读取选通信号和时钟信号产生多个输入控制信号并输出控制信号，并且响应于复位信号被复位，并且管闩锁单元，其响应于输入控制信号锁存输入数据，并响应于输出控制信号输出锁存数据。

9. 发明申请

US20090230996A1 Driving strength control circuit and data output circuit in semiconductor device 有权
标题翻译：半导体器件中的驱动强度控制电路和数据输出电路
公开(公告)号：US20090230996A1
公开(公告)日：2009-09-17
申请号：US12215722
申请日：2008-06-30
申请人： Bok Rim Ko , Youk Hee Kim
发明人： Bok Rim Ko , Youk Hee Kim
IPC分类号： H03K3/00
CPC分类号： H03K19/018585
摘要： A driving strength control circuit and a data output circuit for controlling driving strength of a data driver based on a user's demand are provided to make it possible to control the driving strength through a fuse cutting. The driving strength control circuit includes a fuse signal generating unit for generating a fuse signal based on a fuse cutting, a select signal generating unit for generating select signals in response to the fuse signal, a driving control signal generating unit for receiving set-up signals and generate driving control signals in response to the select signals, and a driving signal generating unit for driving signals by decoding the driving control signals.
摘要翻译：提供了驱动强度控制电路和数据输出电路，用于根据用户的要求来控制数据驱动器的驱动强度，以便通过熔丝切割来控制驱动强度。驱动强度控制电路包括用于根据熔丝切断产生熔丝信号的熔丝信号产生单元，用于响应于熔丝信号产生选择信号的选择信号产生单元，用于接收建立信号的驱动控制信号产生单元并且响应于选择信号产生驱动控制信号;以及驱动信号产生单元，用于通过解码驱动控制信号来驱动信号。

10. 发明申请

US20090002029A1 TEST CONTROL CIRCUIT AND REFERENCE VOLTAGE GENERATING CIRCUIT HAVING THE SAME 有权
标题翻译：测试控制电路和参考电压产生电路
公开(公告)号：US20090002029A1
公开(公告)日：2009-01-01
申请号：US11963463
申请日：2007-12-21
申请人： Youk Hee Kim
发明人： Youk Hee Kim
IPC分类号： H03K19/0175
CPC分类号： G01R31/31724 , G01R31/3004
摘要： A test control circuit according to an embodiment of the invention includes a test mode control unit that outputs a control signal according to a voltage trimming test signal, a decoding portion that receives the control signal and outputs a decoding signal, and a trimming signal adjusting portion that receives the decoding signal and outputs a trimming signal adjusted by a low level test signal.
摘要翻译：根据本发明的实施例的测试控制电路包括测试模式控制单元，其根据电压调整测试信号输出控制信号，接收控制信号并输出解码信号的解码部分和修整信号调整部分其接收解码信号并输出由低电平测试信号调整的微调信号。

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