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1. 发明授权

US06726545B2 Linear polishing for improving substrate uniformity 失效
标题翻译：线性抛光，提高基体均匀性
公开(公告)号：US06726545B2
公开(公告)日：2004-04-27
申请号：US10134821
申请日：2002-04-26
申请人： Subramanian Balakumar , Chen Feng , Victor Lim , Paul Proctor , Mukhopadhyay Madhusudan , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
发明人： Subramanian Balakumar , Chen Feng , Victor Lim , Paul Proctor , Mukhopadhyay Madhusudan , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
IPC分类号： B24B100
CPC分类号： B24B37/16 , B24B21/10 , B24B37/245
摘要： A linear polishing apparatus for polishing a semiconductor substrate including a novel polishing belt arrangement with at least two polishing belts forming a continuous loop. Each belt having an outside polishing surface and an inside smooth surface. The belts are spaced alongside each other sharing a common axis at each end. The belts are looped around a pair of rollers making up a driver roller at one end and a driven roller at the other end. A platen member interposes each belt and is placed between the pairs of rollers. The platen provides a polishing plane and supporting surface for the polishing belts. The polishing plane includes a plurality of holes communicating with an elongated plenum chamber underlying the plane. The chamber supplies a compressed gas to impart an upward pressure against the polishing belts. The driver rollers are coupled to separate motors to independently drive and control at least said two of the polishing belts.
摘要翻译：一种用于抛光包括具有形成连续环的至少两个抛光带的新型抛光带装置的半导体衬底的线性抛光装置。每个带具有外部抛光表面和内部光滑表面。皮带沿着彼此间隔开，在每一端共享公共轴线。皮带环绕一对辊组成一端的驱动辊和另一端的从动辊。压板构件插入每个带并且放置在成对的辊之间。压板提供抛光平面和抛光带的支撑表面。抛光平面包括与平面下方的细长的增压室连通的多个孔。该室供应压缩气体以向抛光带施加向上的压力。驱动辊连接到单独的马达以独立地驱动和控制至少所述两个抛光带。

2. 发明授权

US06248006B1 CMP uniformity 失效
标题翻译： CMP均匀性
公开(公告)号：US06248006B1
公开(公告)日：2001-06-19
申请号：US09490155
申请日：2000-01-24
申请人： Madhusudan Mukhopadhyay , Subramanian Balakumar , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
发明人： Madhusudan Mukhopadhyay , Subramanian Balakumar , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
IPC分类号： B24B508
CPC分类号： B24B37/20 , B24B37/26 , B24B57/02
摘要： A new apparatus is provided that allows for uniform polishing of semiconductor surfaces. The single polishing pad of conventional CMP methods is divided into a split pad, the split pad allows for separate adjustments of CMP control parameters across the surface of the wafer. These adjustments can extend from the center of the wafer to its perimeter (along the radius of the wafer) thereby allowing for the elimination of conventional problems of non-uniformity of polishing between the center of the surface that is polished and the perimeter of the surface that is polished.
摘要翻译：提供了允许半导体表面的均匀抛光的新设备。传统CMP方法的单个抛光垫被分成分裂垫，分离垫允许跨晶片表面的CMP控制参数的单独调整。这些调整可以从晶片的中心延伸到其周边（沿着晶片的半径），从而可以消除抛光表面的中心与表面周边之间的抛光不均匀的常规问题那是抛光。

3. 发明授权

US07095073B2 High K artificial lattices for capacitor applications to use in Cu or Al BEOL 有权
标题翻译：用于电容器应用的高K人造晶格用于Cu或Al BEOL
公开(公告)号：US07095073B2
公开(公告)日：2006-08-22
申请号：US10972551
申请日：2004-10-25
申请人： Subramanian Balakumar , Chew Hoe Ang , Jia Zhen Zheng , Paul Proctor
发明人： Subramanian Balakumar , Chew Hoe Ang , Jia Zhen Zheng , Paul Proctor
IPC分类号： H01L29/76
CPC分类号： H01L28/56 , H01L21/3141 , H01L21/3142 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L28/90
摘要： An improved and new process of fabricating high dielectric constant MIM capacitors. These high dielectric constant MIM capacitor met all of the stringent requirements needed for both for both RF and analog circuit applications. For the high dielectric constant MIM capacitor, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of layers either 4/4, 2/2, and 1/1 artificial layers. Hence thickness of the film can be easily controlled. Enhancement of dielectric constant is because of interface. Dielectric constants near 900 can be easily achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques is used for this type layer growth process.
摘要翻译：一种制造高介电常数MIM电容器的改进和新工艺。这些高介电常数MIM电容器满足RF和模拟电路应用两者所需的所有严格要求。对于高介电常数MIM电容器，金属在双镶嵌工艺中由铜电极组成。超级晶格的介电常数与总体厚度的关系由4/4，2/2和1/1人造层的层数控制。因此，可以容易地控制膜的厚度。介电常数的增强是由于界面。接近900的介电常数可以很容易地达到250埃厚的超晶格。 MBE，分子束外延或ALCVD，原子层CVD技术用于这种类型的层生长过程。

4. 发明授权

US06663472B2 Multiple step CMP polishing 失效
公开(公告)号：US06663472B2
公开(公告)日：2003-12-16
申请号：US10062656
申请日：2002-02-01
申请人： Victor Seng-Keong Lim , Chen Feng , Subramanian Balakumar , Paul Proctor
发明人： Victor Seng-Keong Lim , Chen Feng , Subramanian Balakumar , Paul Proctor
IPC分类号： B24B508
CPC分类号： B24B37/26 , B24B57/02
摘要： An improved chemical mechanical polishing apparatus for planarizing semiconductor surface materials. The single rotating polishing platen with an attached pad of conventional CMP processes is replaced with two controlled independently driven, concentric and coplanar, polishing platens. The two co-planar polishing platens allows for separate adjustable options to the CMP polishing process. The options are provided by having pads of different material compositions and hardness. Moreover, an annular space is provided between the platens to introduce the usage of two slurry formulations, one to each pad, on the same CMP tool. The annular space between platens forming a drain path for catching and containing slurry waste.

5. 发明授权

US06569770B2 Method for improving oxide erosion of tungsten CMP operations 有权
标题翻译：改善钨CMP操作的氧化物侵蚀的方法
公开(公告)号：US06569770B2
公开(公告)日：2003-05-27
申请号：US09893080
申请日：2001-06-28
申请人： Xian Bin Wang , Yi Xu , Subramanian Balakumar , Cuiyang Wang
发明人： Xian Bin Wang , Yi Xu , Subramanian Balakumar , Cuiyang Wang
IPC分类号： H01L2100
CPC分类号： H01L21/7684 , H01L21/3212
摘要： A new method to prevent oxide erosion in a metal plug process by employing a silicon nitride layer over the oxide is described. An oxide layer is deposited overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the oxide layer. An opening is etched through the silicon nitride layer and into the oxide layer. A barrier metal layer is deposited overlying the silicon nitride layer and into the opening. A metal layer is deposited overlying the barrier metal layer. The metal layer and barrier metal layer are polished away using chemical mechanical polishing (CMP) with a polish stop at the silicon nitride layer. The metal layer forms a metal plug. The silicon nitride layer prevents erosion of the oxide layer during the polishing step to complete formation of a metal plug in the fabrication of an integrated circuit device.
摘要翻译：描述了通过在氧化物上使用氮化硅层来防止金属塞过程中的氧化物侵蚀的新方法。沉积在半导体衬底上的氧化物层。沉积氮化硅层覆盖在氧化物层上。通过氮化硅层蚀刻开口并进入氧化物层。在氮化硅层上沉积阻挡金属层并进入开口。沉积在阻挡金属层上的金属层。使用化学机械抛光（CMP）在氮化硅层上抛光停止来抛光金属层和阻挡金属层。金属层形成金属塞。氮化硅层在抛光步骤期间防止氧化物层的侵蚀，以在集成电路器件的制造中完成金属插塞的形成。

6. 发明申请

US20050118780A1 High K artificial lattices for capacitor applications to use in Cu or Al BEOL 有权
标题翻译：用于电容器应用的高K人造晶格用于Cu或Al BEOL
公开(公告)号：US20050118780A1
公开(公告)日：2005-06-02
申请号：US10972551
申请日：2004-10-25
申请人： Subramanian Balakumar , Chew Ang , Jia Zheng , Paul Proctor
发明人： Subramanian Balakumar , Chew Ang , Jia Zheng , Paul Proctor
IPC分类号： H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8234 , H01L21/8244 , H01L21/8242 , H01L21/20
CPC分类号： H01L28/56 , H01L21/3141 , H01L21/3142 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L28/90
摘要： An improved and new process of fabricating high dielectric constant MIM capacitors. These high dielectric constant MIM capacitor met all of the stringent requirements needed for both for both RF and analog circuit applications. For the high dielectric constant MIM capacitor, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of layers either 4/4, 2/2, and 1/1 artificial layers. Hence thickness of the film can be easily controlled. Enhancement of dielectric constant is because of interface. Dielectric constants near 900 can be easily achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques is used for this type layer growth process
摘要翻译：一种制造高介电常数MIM电容器的改进和新工艺。这些高介电常数MIM电容器满足RF和模拟电路应用两者所需的所有严格要求。对于高介电常数MIM电容器，金属由双重镶嵌工艺中的铜电极组成。超级晶格的介电常数与总体厚度的关系由4/4，2/2和1/1人造层的层数控制。因此，可以容易地控制膜的厚度。介电常数的增强是由于界面。接近900的介电常数可以很容易地达到250埃厚的超晶格。 MBE，分子束外延或ALCVD，原子层CVD技术用于这种类型的层生长过程

7. 发明授权

US06830971B2 High K artificial lattices for capacitor applications to use in CU or AL BEOL 有权
标题翻译：用于电容器应用的高K人造晶格用于CU或AL BEOL
公开(公告)号：US06830971B2
公开(公告)日：2004-12-14
申请号：US10286627
申请日：2002-11-02
申请人： Subramanian Balakumar , Chew Hoe Ang , Jia Zhen Zheng , Paul Proctor
发明人： Subramanian Balakumar , Chew Hoe Ang , Jia Zhen Zheng , Paul Proctor
IPC分类号： H01L218242
CPC分类号： H01L28/56 , H01L21/3141 , H01L21/3142 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L28/90
摘要： A process of fabricating high dielectric constant MIM capacitors. The high dielectric constant MIM capacitors are for both RF and analog circuit applications. For the high dielectric constant MIM capacitors, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of artificial layers. Dielectric constants near 900 can be achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques are employed for the layer growth processes.
摘要翻译：制造高介电常数MIM电容器的工艺。高介电常数MIM电容器适用于RF和模拟电路应用。对于高介电常数MIM电容器，金属由双重镶嵌工艺中的铜电极组成。超级晶格的介电常数与总厚度的关系由人造层的数量来控制。接近900的介电常数可以达到250埃厚的超晶格。 MBE，分子束外延或ALCVD，原子层CVD技术用于层生长过程。

8. 发明授权

US06649486B1 Method to form shallow trench isolations 有权
标题翻译：形成浅沟槽隔离的方法
公开(公告)号：US06649486B1
公开(公告)日：2003-11-18
申请号：US09679510
申请日：2000-10-06
申请人： Subramanian Balakumar , Kong Hean Lee , Zheng Zhou , Xian Bin Wang
发明人： Subramanian Balakumar , Kong Hean Lee , Zheng Zhou , Xian Bin Wang
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A new method of fabricating shallow trench isolations has been achieved. A pad oxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A protective layer is deposited overlying the silicon nitride layer. The protective layer, the silicon nitride layer, and the pad oxide layer are patterned to expose the semiconductor substrate where shallow trench isolations are planned. The semiconductor substrate is etched to form trenches for the planned shallow trench isolations. A large trench etching angle is used. The presence of the protective layer prevents loss of the silicon nitride layer during the etching. A trench filling layer is deposited overlying the protective layer and filling the trenches. The trench filling layer and the protective layer are polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.
摘要翻译：已经实现了制造浅沟槽隔离的新方法。在半导体衬底上形成焊盘氧化物层。在衬垫氧化物层上沉积氮化硅层。覆盖氮化硅层的保护层被沉积。对保护层，氮化硅层和焊盘氧化物层进行图案化以暴露其中规划浅沟槽隔离的半导体衬底。蚀刻半导体衬底以形成用于规划的浅沟槽隔离的沟槽。使用大的沟槽蚀刻角度。保护层的存在防止在蚀刻期间氮化硅层的损失。沉积沟槽填充层，覆盖保护层并填充沟槽。在集成电路器件的制造中，沟槽填充层和保护层被抛光以完成浅沟槽隔离。

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