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1. 发明授权

US06663472B2 Multiple step CMP polishing 失效
公开(公告)号：US06663472B2
公开(公告)日：2003-12-16
申请号：US10062656
申请日：2002-02-01
申请人： Victor Seng-Keong Lim , Chen Feng , Subramanian Balakumar , Paul Proctor
发明人： Victor Seng-Keong Lim , Chen Feng , Subramanian Balakumar , Paul Proctor
IPC分类号： B24B508
CPC分类号： B24B37/26 , B24B57/02
摘要： An improved chemical mechanical polishing apparatus for planarizing semiconductor surface materials. The single rotating polishing platen with an attached pad of conventional CMP processes is replaced with two controlled independently driven, concentric and coplanar, polishing platens. The two co-planar polishing platens allows for separate adjustable options to the CMP polishing process. The options are provided by having pads of different material compositions and hardness. Moreover, an annular space is provided between the platens to introduce the usage of two slurry formulations, one to each pad, on the same CMP tool. The annular space between platens forming a drain path for catching and containing slurry waste.

2. 发明授权

US06673695B1 STI scheme to prevent fox recess during pre-CMP HF dip 失效
标题翻译： STI方案，以防止在前CMP HF浸渍期间的狐狸凹陷
公开(公告)号：US06673695B1
公开(公告)日：2004-01-06
申请号：US10062657
申请日：2002-02-01
申请人： Victor Seng-Keong Lim , Paul Proctor
发明人： Victor Seng-Keong Lim , Paul Proctor
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224
摘要： A new method is provided for the creation of STI regions. STI trenches are created in the surface of a substrate following conventional processing. A layer of STI oxide is deposited and, using an exposure mask that is a reverse mask of the mask that is used to create the STI pattern, impurity implants are performed into the surface of the deposited layer of STI oxide. In view of these processing conditions, the layer of STI oxide overlying the patterned layer of etch stop material is exposed to the impurity implants. This exposure alters the etch characteristics of the deposited layer of STI oxide where this STI oxide overlies the patterned layer of etch stop material. The etch rate of the impurity exposed STI oxide is increased by the impurity implantation, resulting in an etch overlying the patterned etch stop layer that proceeds considerably faster than the etch of the STI oxide that is deposited overlying the created STI trenches. With the significantly faster etch of the STI oxide where this oxide has been exposed to impurity implantation, the STI oxide removal can be equalized between the STI oxide that overlies the patterned etch stop layer and the oxide that has been deposited over the STI trenches.
摘要翻译：为创建STI区域提供了一种新方法。在常规处理之后，在衬底的表面中产生STI沟槽。沉积一层STI氧化物，并且使用作为用于产生STI图案的掩模的反掩模的曝光掩模，将杂质植入物进行到STI氧化物沉积层的表面。鉴于这些处理条件，覆盖图案化的蚀刻停止材料层的STI氧化物层暴露于杂质注入。该曝光改变STI氧化物沉积层的蚀刻特性，其中该STI氧化物覆盖在图案化的蚀刻停止材料层上。通过杂质注入，杂质暴露的STI氧化物的蚀刻速率增加，导致覆盖图案化的蚀刻停止层的蚀刻显着快于沉积在所创建的STI沟槽上的STI氧化物的蚀刻。通过对这种氧化物暴露于杂质注入的STI氧化物的显着更快的蚀刻，可以在覆盖图案化蚀刻停止层的STI氧化物和已经沉积在STI沟槽上的氧化物之间均衡STI氧化物去除。

3. 发明授权

US07323406B2 Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures 有权
标题翻译：用于高密度翻盖式封装的高粘结焊盘结构和制造该结构的方法
公开(公告)号：US07323406B2
公开(公告)日：2008-01-29
申请号：US11044282
申请日：2005-01-27
申请人： Victor Seng-Keong Lim , Fan Zhang , Jeffrey Lam
发明人： Victor Seng-Keong Lim , Fan Zhang , Jeffrey Lam
IPC分类号： H01L21/44
CPC分类号： H01L24/12 , H01L21/563 , H01L21/76834 , H01L23/556 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02165 , H01L2224/0401 , H01L2224/05016 , H01L2224/05017 , H01L2224/05078 , H01L2224/05568 , H01L2224/05624 , H01L2224/10126 , H01L2224/13022 , H01L2224/13023 , H01L2224/131 , H01L2224/13116 , H01L2224/13565 , H01L2924/00013 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/00014 , H01L2224/13099 , H01L2224/29099 , H01L2924/00 , H01L2224/05552
摘要： A method for making novel elevated bond-pad structures with sidewall spacers is achieved. The elevated bond-pad structures increase the space between the chip and a substrate during flip-chip bonding. The increased spacing results in better under-filling and reduces alpha particle soft errors in the chip. The sidewall spacers restrict the wetting surface for the PbSn solder bumps to the top surface of the bond pads. This results in smaller solder bumps and allows for closer spacings of the array of bonding pads for higher density integrated circuits.
摘要翻译：实现了一种用于制造具有侧壁间隔物的新型高架结合焊盘结构的方法。升高的焊盘结构在倒装芯片接合期间增加了芯片和衬底之间的空间。间距增加导致更好的欠充，并减少芯片中的α粒子软错误。侧壁间隔件将PbSn焊料凸块的润湿表面限制到接合焊盘的顶表面。这导致较小的焊料凸块并且允许用于较高密度集成电路的焊盘阵列的更紧密的间隔。

4. 发明授权

US06531386B1 Method to fabricate dish-free copper interconnects 失效
标题翻译：制造无盘铜互连的方法
公开(公告)号：US06531386B1
公开(公告)日：2003-03-11
申请号：US10072107
申请日：2002-02-08
申请人： Victor Seng-Keong Lim , Simon Chooi , Randall Cha
发明人： Victor Seng-Keong Lim , Simon Chooi , Randall Cha
IPC分类号： H01L214763
CPC分类号： H01L21/76885 , H01L21/76852 , H01L21/76879
摘要： A method of fabricating at least one metal interconnect including the following steps. A structure having at least one exposed conductive structure is provided. A non-stick material layer is formed over the structure and the at least one exposed conductive structure. The non-stick material layer having an upper surface. The non-stick material layer is patterned to form a patterned non-stick material layer having at least one trench therethrough exposing at least a portion of the at least one conductive structure. A metal interconnect is formed in contact with the exposed portion of the at least one conductive structure within the at least one trench wherein the non-stick properties of the patterned non-stick material layer prevent accumulation of the metal comprising the metal interconnect upon the patterned upper surface of the patterned non-stick material layer. The at least one metal interconnect having an upper surface. The patterned non-stick material layer is removed. A planarized dielectric layer is formed over the structure exposing the upper surface of the at least one metal interconnect.
摘要翻译：一种制造至少一种金属互连的方法，包括以下步骤。提供具有至少一个暴露的导电结构的结构。在结构和至少一个暴露的导电结构上形成不粘材料层。不粘材料层具有上表面。将不粘材料层图案化以形成图案化的不粘材料层，其具有通过其暴露出至少一部分导电结构的至少一个沟槽。在所述至少一个沟槽内形成与所述至少一个导电结构的所述暴露部分接触的金属互连，其中所述图案化不粘材料层的不粘性能防止包含所述金属互连的所述金属在图案化图案化不粘材料层的上表面。所述至少一个金属互连具有上表面。去除图案化的不粘材料层。在暴露至少一个金属互连的上表面的结构之上形成平坦化的介电层。

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