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1. 发明申请

US20070285427A1 GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER 审中-公开
标题翻译：图形处理结构使用统一的阴影
公开(公告)号：US20070285427A1
公开(公告)日：2007-12-13
申请号：US11842256
申请日：2007-08-21
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
IPC分类号： G06F15/00
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译：公开了一种采用单一着色器的图形处理架构。该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一多个输入之一。着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器在音序器中

2. 发明申请

US20050200629A1 Graphics processing architecture employing a unified shader 有权
标题翻译：采用统一着色器的图形处理架构
公开(公告)号：US20050200629A1
公开(公告)日：2005-09-15
申请号：US11117863
申请日：2005-04-29
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
IPC分类号： G06T15/00 , G06T15/80 , G06T15/60 , G06T15/50 , G09G5/36
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译：公开了一种采用单一着色器的图形处理架构。该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一多个输入之一。着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器在音序器中

3. 发明申请

US20100231592A1 GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER 审中-公开
标题翻译：图形处理结构使用统一的阴影
公开(公告)号：US20100231592A1
公开(公告)日：2010-09-16
申请号：US12791597
申请日：2010-06-01
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
IPC分类号： G06F15/00 , G06T15/50
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译：公开了一种采用单一着色器的图形处理架构。该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的一个输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作执行所述顶点操作或像素操作之一多个输入之一。着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器在音序器中

4. 发明授权

US07327369B2 Graphics processing architecture employing a unified shader 有权
标题翻译：采用统一着色器的图形处理架构
公开(公告)号：US07327369B2
公开(公告)日：2008-02-05
申请号：US11117863
申请日：2005-04-29
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
IPC分类号： G06F15/00 , G06T1/00
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译：公开了一种采用单一着色器的图形处理架构。该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的一个输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作执行所述顶点操作或像素操作之一多个输入之一。着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器在音序器中

5. 发明申请

US20050110792A1 GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER 有权
标题翻译：图形处理结构使用统一的阴影
公开(公告)号：US20050110792A1
公开(公告)日：2005-05-26
申请号：US10718318
申请日：2003-11-20
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
IPC分类号： G06T15/00 , G06T15/80 , G06T1/00 , G06F15/00
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译：公开了一种采用单一着色器的图形处理架构。该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一多个输入之一。着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器在音序器中

6. 发明授权

US06897871B1 Graphics processing architecture employing a unified shader 有权
公开(公告)号：US06897871B1
公开(公告)日：2005-05-24
申请号：US10718318
申请日：2003-11-20
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
IPC分类号： G06T15/00 , G06T15/80 , G06F15/00 , G06T1/00
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

7. 发明申请

US20110216077A1 GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER 有权
标题翻译：图形处理结构使用统一的阴影
公开(公告)号：US20110216077A1
公开(公告)日：2011-09-08
申请号：US13109738
申请日：2011-05-17
申请人： Stephen Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Stephen Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
IPC分类号： G06F15/00 , G06T1/00
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译：公开了一种采用单一着色器的图形处理架构。该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的一个输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作执行所述顶点操作或像素操作之一多个输入之一。着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器在音序器中

8. 发明授权

US08760454B2 Graphics processing architecture employing a unified shader 有权
标题翻译：采用统一着色器的图形处理架构
公开(公告)号：US08760454B2
公开(公告)日：2014-06-24
申请号：US13109738
申请日：2011-05-17
申请人： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
发明人： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
IPC分类号： G06F15/00
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data b a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
摘要翻译：一个示例中的图形处理架构通过将顶点数据发送到通用寄存器块来执行顶点操作操作和像素操作操作，并且对顶点数据ba处理器执行顶点操作，除非通用寄存器块在其中没有足够的可用空间存储传入的顶点数据; 并且继续基于在指令存储器中保持的指令来处理或正在执行处理器的像素计算操作，直到通用寄存器块中的足够的寄存器变得可用为止。

9. 发明授权

US09304772B2 Ordering thread wavefronts instruction operations based on wavefront priority, operation counter, and ordering scheme 有权
标题翻译：基于波前优先级，操作计数器和排序方案订购线程波前指令操作
公开(公告)号：US09304772B2
公开(公告)日：2016-04-05
申请号：US13433939
申请日：2012-03-29
申请人： Laurent Lefebvre , Michael Mantor
发明人： Laurent Lefebvre , Michael Mantor
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/38 , G06F9/30 , G06F9/3836 , G06F9/3851 , G06F9/3885 , G06F9/3887
摘要： A system and method is provided for improving efficiency, power, and bandwidth consumption in parallel processing. Rather than requiring memory polling to ensure ordered execution of processes or threads in wavefronts, the techniques disclosed herein provide a system and method to allow any process or thread in a wavefront to run out of order as long as needed, but ensure ordered execution of multiple ordered instructions when needed. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.
摘要翻译：提供了一种用于提高并行处理中的效率，功率和带宽消耗的系统和方法。不需要内存轮询来确保波前的进程或线程的有序执行，本文公开的技术提供一种系统和方法，以允许波阵面中的任何进程或线程在需要时长时间运行，但确保有序执行多个有需要时的指示。这些操作在硬件中有效地处理，但是具有足够的灵活性，可以在各种编程模型中实现。

10. 发明授权

US08400459B2 Multi-thread graphics processing system 有权
标题翻译：多线程图形处理系统
公开(公告)号：US08400459B2
公开(公告)日：2013-03-19
申请号：US11746446
申请日：2007-05-09
申请人： Laurent Lefebvre , Andrew E. Gruber , Stephen L. Morein
发明人： Laurent Lefebvre , Andrew E. Gruber , Stephen L. Morein
IPC分类号： G06T1/00 , G06T1/20 , G06F13/18
CPC分类号： G06T1/20 , G06F9/3851 , G06T1/60 , G06T15/005 , G06T15/04 , G09G5/001 , G09G5/363
摘要： A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
摘要翻译：图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。提供耦合到所述至少一个存储器件的仲裁器，其从所述多个像素命令线程中选择像素命令线程，以及从所述多个顶点命令线程中选择顶点命令线程。仲裁器还从先前选择的像素命令线程和顶点命令线程中选择命令线程，该命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。

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